Main
System Language | VarStore: PlatformLang | VarOffset: 0x0 | Size: 0x2
: 0x0
: 0x1
Advanced
ATS 1 | VarStore: Setup | VarOffset: 0x11 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Advanced
Early Video Logo | VarStore: Setup | VarOffset: 0xF33 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Advanced
Early Console Logo | VarStore: Setup | VarOffset: 0xF34 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Advanced
Package C-State Workaround | VarStore: Setup | VarOffset: 0xF88 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
PTID Support | VarStore: Setup | VarOffset: 0x23
RC ACPI Settings
PECI Access Method | VarStore: Setup | VarOffset: 0x2F | Size: 0x1
Direct I/O: 0x0
ACPI: 0x1
RC ACPI Settings
Native PCIE Enable | VarStore: Setup | VarOffset: 0x21 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
Native ASPM | VarStore: Setup | VarOffset: 0x22 | Size: 0x1
Auto: 0x2
Enabled: 0x1
Disabled: 0x0
RC ACPI Settings
Wake System from S5 | VarStore: Setup | VarOffset: 0x2A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
ACPI Debug | VarStore: Setup | VarOffset: 0x24 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
Print to Serial Port | VarStore: Setup | VarOffset: 0x516 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
Low Power S0 Idle Capability | VarStore: Setup | VarOffset: 0x30 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
PUIS Enable | VarStore: Setup | VarOffset: 0x53A | Size: 0x1
Enabled: 0x1
Disabled: 0x0
RC ACPI Settings
EC Notification | VarStore: Setup | VarOffset: 0x43 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
EC CS Debug Light | VarStore: Setup | VarOffset: 0x44 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
EC Low Power Mode | VarStore: Setup | VarOffset: 0x45 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
Sensor Standby | VarStore: Setup | VarOffset: 0x54 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
CS PL1 Limit | VarStore: Setup | VarOffset: 0x55 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
CS PL1 Value | VarStore: Setup | VarOffset: 0x56 | Size: 0x2
Min: 0xBB8 | Max: 0x4E20 | Step: 0x7D
RC ACPI Settings
Lpit Residency Counter | VarStore: Setup | VarOffset: 0x58 | Size: 0x1
SLP S0: 0x0
C10: 0x1
RC ACPI Settings
Intel Ready Mode Technology | VarStore: Setup | VarOffset: 0x59 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
HW Notification | VarStore: Setup | VarOffset: 0x1F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
Intel RMT State | VarStore: Setup | VarOffset: 0x20 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
PCI Delay Optimization | VarStore: Setup | VarOffset: 0x29 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RC ACPI Settings
MSI enabled | VarStore: Setup | VarOffset: 0x4CA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP CPU | VarStore: Setup | VarOffset: 0x31 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP Graphics | VarStore: Setup | VarOffset: 0x32 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP IPU | VarStore: Setup | VarOffset: 0x40 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP SATA | VarStore: Setup | VarOffset: 0x33 | Size: 0x1
No Constraint: 0x0
Adapter D0/F1: 0x1
Raid Volume0: 0x2
Adapter D3: 0x3
PEP Constraints Configuration
PEP enumerated SATA ports | VarStore: Setup | VarOffset: 0x67B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP PCIe Storage | VarStore: Setup | VarOffset: 0x54A | Size: 0x1
No Constraint: 0x0
D0/F1: 0x1
D3: 0x3
PEP Constraints Configuration
PEP PCIe LAN | VarStore: Setup | VarOffset: 0x6B7 | Size: 0x1
No Constraint: 0x0
D0/F1: 0x1
D3: 0x3
PEP Constraints Configuration
PEP PCIe WLAN | VarStore: Setup | VarOffset: 0x6B8 | Size: 0x1
No Constraint: 0x0
D0/F1: 0x1
D3: 0x3
PEP Constraints Configuration
PEP PCIe GFX | VarStore: Setup | VarOffset: 0x6B9 | Size: 0x1
No Constraint: 0x0
D0/F1: 0x1
D3: 0x3
PEP Constraints Configuration
PEP PCIe Other | VarStore: Setup | VarOffset: 0x6BA | Size: 0x1
No Constraint: 0x0
D0/F1: 0x1
D3: 0x3
PEP Constraints Configuration
PEP PCIe DG1 | VarStore: Setup | VarOffset: 0x694 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP UART | VarStore: Setup | VarOffset: 0x34 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP I2C0 | VarStore: Setup | VarOffset: 0x35 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP I2C1 | VarStore: Setup | VarOffset: 0x36 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP I2C2 | VarStore: Setup | VarOffset: 0x37 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP I2C3 | VarStore: Setup | VarOffset: 0x38 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP I2C4 | VarStore: Setup | VarOffset: 0x39 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP I2C5 | VarStore: Setup | VarOffset: 0x3A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP SPI | VarStore: Setup | VarOffset: 0x3B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP XHCI | VarStore: Setup | VarOffset: 0x3C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP Audio | VarStore: Setup | VarOffset: 0x3D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP EMMC | VarStore: Setup | VarOffset: 0x3E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP SDXC | VarStore: Setup | VarOffset: 0x3F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP CSME | VarStore: Setup | VarOffset: 0x41 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP LAN(GBE) | VarStore: Setup | VarOffset: 0x42 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEP Constraints Configuration
PEP TBT RP | VarStore: Setup | VarOffset: 0x689 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Connectivity Configuration
CNVi WiFi&BT | VarStore: PchSetup | VarOffset: 0x6D7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Connectivity Configuration
BT Core | VarStore: PchSetup | VarOffset: 0x6D8 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Connectivity Configuration
BT Audio Offload | VarStore: PchSetup | VarOffset: 0x6D9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Connectivity Configuration
CoExistence Manager | VarStore: Setup | VarOffset: 0x4B5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Connectivity Configuration
Discrete Bluetooth Module | VarStore: Setup | VarOffset: 0x2E8 | Size: 0x1
Disabled: 0x0
Thunder Peak: 0x1
Connectivity Configuration
BT Interrupt Mode | VarStore: Setup | VarOffset: 0x2E9 | Size: 0x1
GPIO Interrupt: 0x0
APIC Interrupt: 0x1
Connectivity Configuration
Advanced settings | VarStore: Setup | VarOffset: 0x45F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Connectivity Configuration
Switched Antenna Diversity Selection | VarStore: Setup | VarOffset: 0x537 | Size: 0x1
Antenna1: 0x0
Antenna2: 0x1
Diversity: 0x2
Diversity Antenna1: 0x3
Diversity Antenna2: 0x4
Connectivity Configuration
Domain Type SPLC 1 | VarStore: Setup | VarOffset: 0x460 | Size: 0x1
Min: 0x0 | Max: 0x14 | Step: 0x1
Connectivity Configuration
Default Power Limit | VarStore: Setup | VarOffset: 0x461 | Size: 0x2
Min: 0x1 | Max: 0xFFFF | Step: 0x1
Connectivity Configuration
Default Time Window | VarStore: Setup | VarOffset: 0x463 | Size: 0x4
Min: 0x1 | Max: 0x186A0 | Step: 0x1
Connectivity Configuration
TRxDelay_A | VarStore: Setup | VarOffset: 0x467 | Size: 0x1
Min: 0x1 | Max: 0x64 | Step: 0x1
Connectivity Configuration
TRxCableLength_A | VarStore: Setup | VarOffset: 0x468 | Size: 0x1
Min: 0x1 | Max: 0x64 | Step: 0x1
Connectivity Configuration
TRxDelay_B | VarStore: Setup | VarOffset: 0x469 | Size: 0x1
Min: 0x1 | Max: 0x64 | Step: 0x1
Connectivity Configuration
TRxCableLength_B | VarStore: Setup | VarOffset: 0x46A | Size: 0x1
Min: 0x1 | Max: 0x64 | Step: 0x1
Connectivity Configuration
Domain Type | VarStore: Setup | VarOffset: 0x46B | Size: 0x1
Min: 0x0 | Max: 0x64 | Step: 0x1
Connectivity Configuration
Country Identifier | VarStore: Setup | VarOffset: 0x46C | Size: 0x2
Min: 0x1 | Max: 0xFFFF | Step: 0x1
Connectivity Configuration
WiFi SAR | VarStore: Setup | VarOffset: 0x471 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Connectivity Configuration
SAR 2400 MHz Set1 Chain A | VarStore: Setup | VarOffset: 0x472 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5150-5350 MHz Set1 Chain A | VarStore: Setup | VarOffset: 0x473 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5350-5470 MHz Set1 Chain A | VarStore: Setup | VarOffset: 0x474 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5470-5725 MHz Set1 Chain A | VarStore: Setup | VarOffset: 0x475 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5725-5950 MHz Set1 Chain A | VarStore: Setup | VarOffset: 0x476 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Set1 Chain B | VarStore: Setup | VarOffset: 0x477 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5150-5350 MHz Set1 Chain B | VarStore: Setup | VarOffset: 0x478 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5350-5470 MHz Set1 Chain B | VarStore: Setup | VarOffset: 0x479 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5470-5725 MHz Set1 Chain B | VarStore: Setup | VarOffset: 0x47A | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5725-5950 MHz Set1 Chain B | VarStore: Setup | VarOffset: 0x47B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
WiFi Dynamic SAR | VarStore: Setup | VarOffset: 0x47C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Connectivity Configuration
Extended SAR Range Sets | VarStore: Setup | VarOffset: 0x47D | Size: 0x1
No Additional sets: 0x0
Set 2: 0x1
Set 3: 0x2
Set 4: 0x3
Connectivity Configuration
SAR 2400 MHz Set2 Chain A | VarStore: Setup | VarOffset: 0x47E | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5150-5350 MHz Set2 Chain A | VarStore: Setup | VarOffset: 0x47F | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5350-5470 MHz Set2 Chain A | VarStore: Setup | VarOffset: 0x480 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5470-5725 MHz Set2 Chain A | VarStore: Setup | VarOffset: 0x481 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5725-5950 MHz Set2 Chain A | VarStore: Setup | VarOffset: 0x482 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Set2 Chain B | VarStore: Setup | VarOffset: 0x483 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5150-5350 MHz Set2 Chain B | VarStore: Setup | VarOffset: 0x484 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5350-5470 MHz Set2 Chain B | VarStore: Setup | VarOffset: 0x485 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5470-5725 MHz Set2 Chain B | VarStore: Setup | VarOffset: 0x486 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5725-5950 MHz Set2 Chain B | VarStore: Setup | VarOffset: 0x487 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Set3 Chain A | VarStore: Setup | VarOffset: 0x488 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5150-5350 MHz Set3 Chain A | VarStore: Setup | VarOffset: 0x489 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5350-5470 MHz Set3 Chain A | VarStore: Setup | VarOffset: 0x48A | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5470-5725 MHz Set3 Chain A | VarStore: Setup | VarOffset: 0x48B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5725-5950 MHz Set3 Chain A | VarStore: Setup | VarOffset: 0x48C | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Set3 Chain B | VarStore: Setup | VarOffset: 0x48D | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5150-5350 MHz Set3 Chain B | VarStore: Setup | VarOffset: 0x48E | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5350-5470 MHz Set3 Chain B | VarStore: Setup | VarOffset: 0x48F | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5470-5725 MHz Set3 Chain B | VarStore: Setup | VarOffset: 0x490 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5725-5950 MHz Set3 Chain B | VarStore: Setup | VarOffset: 0x491 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Set4 Chain A | VarStore: Setup | VarOffset: 0x492 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5150-5350 MHz Set4 Chain A | VarStore: Setup | VarOffset: 0x493 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5350-5470 MHz Set4 Chain A | VarStore: Setup | VarOffset: 0x494 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5470-5725 MHz Set4 Chain A | VarStore: Setup | VarOffset: 0x495 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5725-5950 MHz Set4 Chain A | VarStore: Setup | VarOffset: 0x496 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Set4 Chain B | VarStore: Setup | VarOffset: 0x497 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5150-5350 MHz Set4 Chain B | VarStore: Setup | VarOffset: 0x498 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5350-5470 MHz Set4 Chain B | VarStore: Setup | VarOffset: 0x499 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5470-5725 MHz Set4 Chain B | VarStore: Setup | VarOffset: 0x49A | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5725-5950 MHz Set4 Chain B | VarStore: Setup | VarOffset: 0x49B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Antenna A Current Set | VarStore: Setup | VarOffset: 0x4AE | Size: 0x1
Default OTP table: 0x0
Set 1: 0x1
Set 2: 0x2
Set 3: 0x3
Set 4: 0x4
Connectivity Configuration
Antenna B Current Set | VarStore: Setup | VarOffset: 0x4AF | Size: 0x1
Default OTP table: 0x0
Set 1: 0x1
Set 2: 0x2
Set 3: 0x3
Set 4: 0x4
Connectivity Configuration
SAR 2400 MHz Max Allowed for Group 1 (FCC) | VarStore: Setup | VarOffset: 0x49C | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Chain A Offset for Group 1 (FCC) | VarStore: Setup | VarOffset: 0x49D | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Chain B Offset for Group 1 (FCC) | VarStore: Setup | VarOffset: 0x49E | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5200 MHz Max Allowed for Group 1 (FCC) | VarStore: Setup | VarOffset: 0x49F | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5200 MHz Chain A Offset for Group 1 (FCC) | VarStore: Setup | VarOffset: 0x4A0 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5200 MHz Chain B Offset for Group 1 (FCC) | VarStore: Setup | VarOffset: 0x4A1 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Max Allowed for Group 2 (EU Japan) | VarStore: Setup | VarOffset: 0x4A2 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Chain A Offset for Group 2 (EU Japan) | VarStore: Setup | VarOffset: 0x4A3 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Chain B Offset for Group 2 (EU Japan) | VarStore: Setup | VarOffset: 0x4A4 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5200 MHz Max Allowed for Group 2 (EU Japan) | VarStore: Setup | VarOffset: 0x4A5 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5200 MHz Chain A Offset for Group 2 (EU Japan) | VarStore: Setup | VarOffset: 0x4A6 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5200 MHz Chain B Offset for Group 2 (EU Japan) | VarStore: Setup | VarOffset: 0x4A7 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Max Allowed for Group 3 (ROW) | VarStore: Setup | VarOffset: 0x4A8 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Chain A Offset for Group 3 (ROW) | VarStore: Setup | VarOffset: 0x4A9 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 2400 MHz Chain B Offset for Group 3 (ROW) | VarStore: Setup | VarOffset: 0x4AA | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5200 MHz Max Allowed for Group 3 (ROW) | VarStore: Setup | VarOffset: 0x4AB | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5200 MHz Chain A Offset for Group 3 (ROW) | VarStore: Setup | VarOffset: 0x4AC | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
SAR 5200 MHz Chain B Offset for Group 3 (ROW) | VarStore: Setup | VarOffset: 0x4AD | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Wifi ANT Gain control | VarStore: Setup | VarOffset: 0x67C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Connectivity Configuration
ANT Gain 2400MHz Chain A | VarStore: Setup | VarOffset: 0x67D | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
ANT Gain 5150MHz-5350MHz Chain A | VarStore: Setup | VarOffset: 0x67E | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 5350MHz-5470MHz Chain A | VarStore: Setup | VarOffset: 0x67F | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 5470MHz-5725MHz Chain A | VarStore: Setup | VarOffset: 0x680 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 5725MHZ-5950MHz Chain A | VarStore: Setup | VarOffset: 0x681 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 2400MHz Chain B | VarStore: Setup | VarOffset: 0x682 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 5150MHz-5350MHz Chain B | VarStore: Setup | VarOffset: 0x683 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 5350MHz-5470MHz Chain B | VarStore: Setup | VarOffset: 0x684 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 5470MHz-5725MHz Chain B | VarStore: Setup | VarOffset: 0x685 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Ant Gain 5725MHZ-5950MHz Chain B | VarStore: Setup | VarOffset: 0x686 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
External 32kHz Clock | VarStore: Setup | VarOffset: 0x687 | Size: 0x1
Not Valid: 0x0
Valid: 0x1
Connectivity Configuration
Bluetooth SAR | VarStore: Setup | VarOffset: 0x4B0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Connectivity Configuration
Bluetooth SAR BR | VarStore: Setup | VarOffset: 0x4B1 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Bluetooth SAR EDR2 | VarStore: Setup | VarOffset: 0x4B2 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Bluetooth SAR EDR3 | VarStore: Setup | VarOffset: 0x4B3 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Bluetooth SAR LE | VarStore: Setup | VarOffset: 0x4B4 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Bluetooth SAR LE 2Mhz | VarStore: Setup | VarOffset: 0x538 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Connectivity Configuration
Bluetooth SAR LE LR | VarStore: Setup | VarOffset: 0x539 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
WWAN Configuration
WWAN Device | VarStore: Setup | VarOffset: 0x54C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
WWAN Configuration
WWAN Reset Workaround | VarStore: Setup | VarOffset: 0x688 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
C6DRAM | VarStore: CpuSetup | VarOffset: 0xDF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
Software Guard Extensions (SGX) | VarStore: CpuSetup | VarOffset: 0xE0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Software Controlled: 0x2
CPU Configuration
Select Owner EPOCH Input Type | VarStore: CpuSetup | VarOffset: 0xE1 | Size: 0x1
No Change In Owner EPOCHs: 0x0
Change To New Random Owner EPOCHs: 0x1
Manual User Defined Owner EPOCHs: 0x2
CPU Configuration
Software Guard Extensions Epoch 0 | VarStore: CpuSetupSgxEpochData | VarOffset: 0x0 | Size: 0x8
Min: 0x0 | Max: 0xFFFFFFFFFFFFFFFF | Step: 0x1
CPU Configuration
Software Guard Extensions Epoch 1 | VarStore: CpuSetupSgxEpochData | VarOffset: 0x8 | Size: 0x8
Min: 0x0 | Max: 0xFFFFFFFFFFFFFFFF | Step: 0x1
CPU Configuration
Maximum Supported PRMRR Size | VarStore: CpuSetup | VarOffset: 0xE3 | Size: 0x4
Min: 0x0 | Max: 0xFFFFFFFF | Step: 0x1
CPU Configuration
PRMRR Size | VarStore: CpuSetup | VarOffset: 0xE7 | Size: 0x4
Invalid PRMRR: 0x0
32MB: 0x2000000
64MB: 0x4000000
128MB: 0x8000000
256MB: 0x10000000
CPU Configuration
CPU Flex Ratio Override | VarStore: CpuSetup | VarOffset: 0x3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
CPU Flex Ratio Settings | VarStore: CpuSetup | VarOffset: 0x1 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x0
CPU Configuration
Hardware Prefetcher | VarStore: CpuSetup | VarOffset: 0xBA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
Adjacent Cache Line Prefetch | VarStore: CpuSetup | VarOffset: 0xBB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
Intel (VMX) Virtualization Technology | VarStore: CpuSetup | VarOffset: 0xB4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
PECI | VarStore: CpuSetup | VarOffset: 0x4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
AVX | VarStore: CpuSetup | VarOffset: 0x2D9 | Size: 0x1
Enabled: 0x0
Disabled: 0x1
CPU Configuration
AVX3 | VarStore: CpuSetup | VarOffset: 0x2DA | Size: 0x1
Enabled: 0x0
Disabled: 0x1
CPU Configuration
Active Processor Cores | VarStore: CpuSetup | VarOffset: 0x6 | Size: 0x1
All: 0x0
1: 0x1
2: 0x2
3: 0x3
4: 0x4
5: 0x5
6: 0x6
7: 0x7
8: 0x8
9: 0x9
CPU Configuration
Limit CPUID Maximum | VarStore: CpuSetup | VarOffset: 0x2DC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
Hyper-Threading | VarStore: CpuSetup | VarOffset: 0x5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
BIST | VarStore: CpuSetup | VarOffset: 0x7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
AP threads Idle Manner | VarStore: CpuSetup | VarOffset: 0xFB | Size: 0x1
HALT Loop: 0x1
MWAIT Loop: 0x2
RUN Loop: 0x3
CPU Configuration
AES | VarStore: CpuSetup | VarOffset: 0xB5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
MachineCheck | VarStore: CpuSetup | VarOffset: 0xB6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
MonitorMWait | VarStore: CpuSetup | VarOffset: 0xB7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
Intel Trusted Execution Technology | VarStore: CpuSetup | VarOffset: 0xBC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
Alias Check Request | VarStore: CpuSetup | VarOffset: 0xBF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
DPR Memory Size (MB) | VarStore: CpuSetup | VarOffset: 0xB8 | Size: 0x2
Min: 0x0 | Max: 0xFF | Step: 0x1
CPU Configuration
Reset AUX Content | VarStore: CpuSetup | VarOffset: 0xBE | Size: 0x1
Yes: 0x1
No: 0x0
CPU Configuration
FCLK Frequency For Early Power On | VarStore: CpuSetup | VarOffset: 0x101 | Size: 0x1
Normal (800Mhz): 0x0
1GHz: 0x1
400MHz: 0x2
Auto: 0x3
CPU Configuration
Voltage Optimization | VarStore: CpuSetup | VarOffset: 0x1DB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Auto: 0x2
CPU Configuration
RaceConditionResponse Policy | VarStore: CpuSetup | VarOffset: 0x2DB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
BIOS Guard
Enable Tools Interface | VarStore: CpuSetup | VarOffset: 0xDC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU SMM Enhancement
SMM MSR Save State Enable | VarStore: CpuSmm | VarOffset: 0x0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU SMM Enhancement
SMM Code Access Check | VarStore: CpuSmm | VarOffset: 0x1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU SMM Enhancement
SMM Use Delay Indication | VarStore: CpuSmm | VarOffset: 0x2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU SMM Enhancement
SMM Use Block Indication | VarStore: CpuSmm | VarOffset: 0x3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU SMM Enhancement
SMM Use SMM en-US Indication | VarStore: CpuSmm | VarOffset: 0x4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU SMM Enhancement
DGR+NR11 / NR10 Support | VarStore: CpuSmm | VarOffset: 0x6 | Size: 0x1
NR10: 0x0
DGR_NR11: 0x1
Power & Performance
Intel(R) Speed Shift Technology Interrupt Control | VarStore: CpuSetup | VarOffset: 0x1FC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Boot Performance Mode | VarStore: CpuSetup | VarOffset: 0xE | Size: 0x1
Max Battery: 0x0
Max Non-Turbo Performance: 0x1
Turbo Performance: 0x2
CPU - Power Management Control
Intel(R) SpeedStep(tm) | VarStore: CpuSetup | VarOffset: 0x9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Race To Halt (RTH) | VarStore: CpuSetup | VarOffset: 0xA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Intel(R) Speed Shift Technology | VarStore: CpuSetup | VarOffset: 0xB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Intel(R) Turbo Boost Max Technology 3.0 | VarStore: CpuSetup | VarOffset: 0xC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Intel(R) Adaptive Boost Technology | VarStore: CpuSetup | VarOffset: 0x2D8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Per Core P State OS control mode | VarStore: CpuSetup | VarOffset: 0x262 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
HwP Autonomous Per Core P State | VarStore: CpuSetup | VarOffset: 0x263 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
HwP Autonomous EPP Grouping | VarStore: CpuSetup | VarOffset: 0x264 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
EPB override over PECI | VarStore: CpuSetup | VarOffset: 0x265 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
HwP Fast MSR Support | VarStore: CpuSetup | VarOffset: 0x266 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
HDC Control | VarStore: CpuSetup | VarOffset: 0x45 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Turbo Mode | VarStore: CpuSetup | VarOffset: 0x11 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Platform PL1 Enable | VarStore: CpuSetup | VarOffset: 0x2C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Platform PL1 Power | VarStore: CpuSetup | VarOffset: 0x2D | Size: 0x4
Min: 0x0 | Max: 0x3E7F83 | Step: 0x7D
CPU - Power Management Control
Platform PL1 Time Window | VarStore: CpuSetup | VarOffset: 0x31 | Size: 0x1
0: 0x0
1: 0x1
2: 0x2
3: 0x3
4: 0x4
5: 0x5
6: 0x6
7: 0x7
8: 0x8
10: 0xA
12: 0xC
14: 0xE
16: 0x10
20: 0x14
24: 0x18
28: 0x1C
32: 0x20
40: 0x28
48: 0x30
56: 0x38
64: 0x40
80: 0x50
96: 0x60
112: 0x70
128: 0x80
CPU - Power Management Control
Platform PL2 Enable | VarStore: CpuSetup | VarOffset: 0x32 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Platform PL2 Power | VarStore: CpuSetup | VarOffset: 0x33 | Size: 0x4
Min: 0x0 | Max: 0x3E7F83 | Step: 0x7D
CPU - Power Management Control
Power Limit 4 Override | VarStore: CpuSetup | VarOffset: 0x25 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Power Limit 4 | VarStore: CpuSetup | VarOffset: 0x26 | Size: 0x4
Min: 0x0 | Max: 0xF9F83 | Step: 0x7D
CPU - Power Management Control
Power Limit 4 Lock | VarStore: CpuSetup | VarOffset: 0x2A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
C-States | VarStore: CpuSetup | VarOffset: 0xF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Enhanced C-States | VarStore: CpuSetup | VarOffset: 0x10 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
C-State Auto Demotion | VarStore: CpuSetup | VarOffset: 0x39 | Size: 0x1
Disabled: 0x0
C1: 0x1
C3: 0x2
C1 and C3: 0x3
CPU - Power Management Control
C-State Un-Demotion | VarStore: CpuSetup | VarOffset: 0x3A | Size: 0x1
Disabled: 0x0
C1: 0x1
C3: 0x2
C1 and C3: 0x3
CPU - Power Management Control
Package C-State Demotion | VarStore: CpuSetup | VarOffset: 0x3B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Package C-State Un-Demotion | VarStore: CpuSetup | VarOffset: 0x3C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
C-State Pre-Wake | VarStore: CpuSetup | VarOffset: 0x38 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
IO MWAIT Redirection | VarStore: CpuSetup | VarOffset: 0x43 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Package C-State Limit | VarStore: CpuSetup | VarOffset: 0x46 | Size: 0x1
C0/C1: 0x0
C2: 0x1
C3: 0x2
C6: 0x3
C7: 0x4
C7S: 0x5
C8: 0x6
C9: 0x7
C10: 0x8
Cpu Default: 0xFE
Auto: 0xFF
CPU - Power Management Control
Time Unit | VarStore: CpuSetup | VarOffset: 0x22E | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
CPU - Power Management Control
Latency | VarStore: CpuSetup | VarOffset: 0x22F | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
CPU - Power Management Control
Time Unit | VarStore: CpuSetup | VarOffset: 0x47 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
CPU - Power Management Control
Latency | VarStore: CpuSetup | VarOffset: 0x4C | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
CPU - Power Management Control
Time Unit | VarStore: CpuSetup | VarOffset: 0x48 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
CPU - Power Management Control
Latency | VarStore: CpuSetup | VarOffset: 0x4E | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
CPU - Power Management Control
Time Unit | VarStore: CpuSetup | VarOffset: 0x49 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
CPU - Power Management Control
Latency | VarStore: CpuSetup | VarOffset: 0x50 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
CPU - Power Management Control
Time Unit | VarStore: CpuSetup | VarOffset: 0x4A | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
CPU - Power Management Control
Latency | VarStore: CpuSetup | VarOffset: 0x52 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
CPU - Power Management Control
Time Unit | VarStore: CpuSetup | VarOffset: 0x4B | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
CPU - Power Management Control
Latency | VarStore: CpuSetup | VarOffset: 0x54 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
CPU - Power Management Control
Thermal Monitor | VarStore: CpuSetup | VarOffset: 0x3D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Interrupt Redirection Mode Selection | VarStore: CpuSetup | VarOffset: 0x44 | Size: 0x1
Fixed Priority: 0x0
Round robin: 0x1
Hash Vector: 0x2
PAIR with Fixed Priority: 0x4
PAIR with Round Robin: 0x5
PAIR with Hash Vector: 0x6
No Change: 0x7
CPU - Power Management Control
Timed MWAIT | VarStore: CpuSetup | VarOffset: 0x42 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
EC Turbo Control Mode | VarStore: CpuSetup | VarOffset: 0xC2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
AC Brick Capacity | VarStore: CpuSetup | VarOffset: 0xC3 | Size: 0x1
90W AC Brick: 0x1
65W AC Brick: 0x2
75W AC Brick: 0x3
CPU - Power Management Control
EC Polling Period | VarStore: CpuSetup | VarOffset: 0xC4 | Size: 0x1
Min: 0x1 | Max: 0xFF | Step: 0x1
CPU - Power Management Control
EC Guard Band Value | VarStore: CpuSetup | VarOffset: 0xC5 | Size: 0x1
Min: 0x0 | Max: 0x14 | Step: 0x1
CPU - Power Management Control
EC Algorithm Selection | VarStore: CpuSetup | VarOffset: 0xC6 | Size: 0x1
Min: 0x1 | Max: 0xA | Step: 0x1
CPU - Power Management Control
Energy Performance Gain | VarStore: SaSetup | VarOffset: 0xF2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
EPG DIMM Idd3N | VarStore: SaSetup | VarOffset: 0xF3 | Size: 0x2
Min: 0x0 | Max: 0x7D0 | Step: 0x1
CPU - Power Management Control
EPG DIMM Idd3P | VarStore: SaSetup | VarOffset: 0xF5 | Size: 0x2
Min: 0x0 | Max: 0x7D0 | Step: 0x1
CPU - Power Management Control
Dual Tau Boost | VarStore: CpuSetup | VarOffset: 0x24D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Custom P-state Table
Number of P states | VarStore: CpuSetup | VarOffset: 0x7B | Size: 0x1
Min: 0x0 | Max: 0x28 | Step: 0x0
Custom P-state Table
Max P-State Ratio | VarStore: CpuSetup | VarOffset: 0x7C | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x7D | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x7E | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x7F | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x80 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x81 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x82 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x83 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x84 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x85 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x86 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x87 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x88 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x89 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x8A | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x8B | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x8C | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x8D | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x8E | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x8F | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x90 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x91 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x92 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x93 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x94 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x95 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x96 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x97 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x98 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x99 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x9A | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x9B | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x9C | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x9D | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x9E | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0x9F | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0xA0 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0xA1 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0xA2 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio | VarStore: CpuSetup | VarOffset: 0xA3 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
Max P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xA4 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xA5 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xA6 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xA7 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xA8 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xA9 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xAA | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xAB | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xAC | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xAD | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xAE | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xAF | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xB0 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xB1 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xB2 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
Custom P-state Table
Min P-State Ratio (Max 16 table) | VarStore: CpuSetup | VarOffset: 0xB3 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
View/Configure Turbo Options
Energy Efficient P-state | VarStore: CpuSetup | VarOffset: 0x37 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
View/Configure Turbo Options
Package Power Limit MSR Lock | VarStore: CpuSetup | VarOffset: 0x2B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
View/Configure Turbo Options
Power Limit 1 Override | VarStore: CpuSetup | VarOffset: 0x16 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
View/Configure Turbo Options
Power Limit 1 | VarStore: CpuSetup | VarOffset: 0x12 | Size: 0x4
Min: 0x0 | Max: 0x3E7F83 | Step: 0x7D
View/Configure Turbo Options
Power Limit 1 Time Window | VarStore: CpuSetup | VarOffset: 0x17 | Size: 0x1
0: 0x0
1: 0x1
2: 0x2
3: 0x3
4: 0x4
5: 0x5
6: 0x6
7: 0x7
8: 0x8
10: 0xA
12: 0xC
14: 0xE
16: 0x10
20: 0x14
24: 0x18
28: 0x1C
32: 0x20
40: 0x28
48: 0x30
56: 0x38
64: 0x40
80: 0x50
96: 0x60
112: 0x70
128: 0x80
View/Configure Turbo Options
Power Limit 2 Override | VarStore: CpuSetup | VarOffset: 0x18 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
View/Configure Turbo Options
Power Limit 2 | VarStore: CpuSetup | VarOffset: 0x19 | Size: 0x4
Min: 0x0 | Max: 0x3E7F83 | Step: 0x7D
View/Configure Turbo Options
Turbo Ratio Limit Core0 (TRLC) | VarStore: CpuSetup | VarOffset: 0x243 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
View/Configure Turbo Options
Turbo Ratio Limit Core1 (TRLC) | VarStore: CpuSetup | VarOffset: 0x244 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
View/Configure Turbo Options
Turbo Ratio Limit Core2 (TRLC) | VarStore: CpuSetup | VarOffset: 0x245 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
View/Configure Turbo Options
Turbo Ratio Limit Core3 (TRLC) | VarStore: CpuSetup | VarOffset: 0x246 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
View/Configure Turbo Options
Turbo Ratio Limit Core4 (TRLC) | VarStore: CpuSetup | VarOffset: 0x247 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
View/Configure Turbo Options
Turbo Ratio Limit Core5 (TRLC) | VarStore: CpuSetup | VarOffset: 0x248 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
View/Configure Turbo Options
Turbo Ratio Limit Core6 (TRLC) | VarStore: CpuSetup | VarOffset: 0x249 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
View/Configure Turbo Options
Turbo Ratio Limit Core7 (TRLC) | VarStore: CpuSetup | VarOffset: 0x24A | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
View/Configure Turbo Options
Turbo Ratio Limit Ratio0 (TRLR) | VarStore: CpuSetup | VarOffset: 0xD1 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
View/Configure Turbo Options
Turbo Ratio Limit Ratio1 (TRLR) | VarStore: CpuSetup | VarOffset: 0xD2 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
View/Configure Turbo Options
Turbo Ratio Limit Ratio2 (TRLR) | VarStore: CpuSetup | VarOffset: 0xD3 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
View/Configure Turbo Options
Turbo Ratio Limit Ratio3 (TRLR) | VarStore: CpuSetup | VarOffset: 0xD4 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
View/Configure Turbo Options
Turbo Ratio Limit Ratio4 (TRLR) | VarStore: CpuSetup | VarOffset: 0xD5 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
View/Configure Turbo Options
Turbo Ratio Limit Ratio5 (TRLR) | VarStore: CpuSetup | VarOffset: 0xD6 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
View/Configure Turbo Options
Turbo Ratio Limit Ratio6 (TRLR) | VarStore: CpuSetup | VarOffset: 0xD7 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
View/Configure Turbo Options
Turbo Ratio Limit Ratio7 (TRLR) | VarStore: CpuSetup | VarOffset: 0xD8 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
View/Configure Turbo Options
Energy Efficient Turbo | VarStore: CpuSetup | VarOffset: 0x1AF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Auto: 0x2
CPU VR Settings
VR Power Delivery Design | VarStore: CpuSetup | VarOffset: 0x23A | Size: 0x1
AUTO: 0x0
CML S 2+2 35W: 0x1
CML S 2+2 58W: 0x2
CML S 2+2 65W: 0x3
CML S 4+2 35W: 0x4
CML S 4+2 65W: 0x5
CML S 6+2 35W: 0x6
CML S 6+2 65W: 0x7
CML S 6+2 80W: 0x8
CML S 6+2 125W: 0x9
CML S 8+2 35W: 0xA
CML S 8+2 65W: 0xB
CML S 8+2 80W: 0xC
CML S 8+2 125W: 0xD
CML S 10+2 35W: 0xE
CML S 10+2 65W: 0xF
CML S 10+2 80W: 0x10
CML S 10+2 95W: 0x11
CML S 10+2 125W: 0x12
CML H 4+2 45W: 0x13
CML H 6+2 45W: 0x14
CML H 8+2 45W: 0x15
CPU VR Settings
PSYS Slope | VarStore: CpuSetup | VarOffset: 0x102 | Size: 0x1
Min: 0x0 | Max: 0xC8 | Step: 0x1
CPU VR Settings
PSYS Offset | VarStore: CpuSetup | VarOffset: 0x103 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
CPU VR Settings
PSYS PMax Power | VarStore: CpuSetup | VarOffset: 0x104 | Size: 0x2
Min: 0x0 | Max: 0x1FFF | Step: 0x1
CPU VR Settings
Intersil VR Command | VarStore: CpuSetup | VarOffset: 0x209 | Size: 0x1
Disabled: 0x0
Send for IA/GT rails: 0x1
Send for IA/GT/SA rails: 0x2
Acoustic Noise Settings
Acoustic Noise Mitigation | VarStore: CpuSetup | VarOffset: 0x1F3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Acoustic Noise Settings
Pre Wake Time | VarStore: CpuSetup | VarOffset: 0x237 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Acoustic Noise Settings
Ramp Up Time | VarStore: CpuSetup | VarOffset: 0x238 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Acoustic Noise Settings
Ramp Down Time | VarStore: CpuSetup | VarOffset: 0x239 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Acoustic Noise Settings
Disable Fast PKG C State Ramp for IA Domain | VarStore: CpuSetup | VarOffset: 0x1F4 | Size: 0x1
FALSE: 0x0
TRUE: 0x1
Acoustic Noise Settings
Slow Slew Rate for IA Domain | VarStore: CpuSetup | VarOffset: 0x1F8 | Size: 0x1
Fast/2: 0x0
Fast/4: 0x1
Fast/8: 0x2
Fast/16: 0x3
Acoustic Noise Settings
Disable Fast PKG C State Ramp for GT Domain | VarStore: CpuSetup | VarOffset: 0x1F5 | Size: 0x1
FALSE: 0x0
TRUE: 0x1
Acoustic Noise Settings
Slow Slew Rate for GT Domain | VarStore: CpuSetup | VarOffset: 0x1F9 | Size: 0x1
Fast/2: 0x0
Fast/4: 0x1
Fast/8: 0x2
Fast/16: 0x3
Acoustic Noise Settings
Disable Fast PKG C State Ramp for SA Domain | VarStore: CpuSetup | VarOffset: 0x1F6 | Size: 0x1
FALSE: 0x0
TRUE: 0x1
Acoustic Noise Settings
Slow Slew Rate for SA Domain | VarStore: CpuSetup | VarOffset: 0x1FA | Size: 0x1
Fast/2: 0x0
Fast/4: 0x1
Fast/8: 0x2
Acoustic Noise Settings
Disable Fast PKG C State Ramp for VccIn Domain | VarStore: CpuSetup | VarOffset: 0x1F7 | Size: 0x1
FALSE: 0x0
TRUE: 0x1
Acoustic Noise Settings
Slow Slew Rate for VccIn Domain | VarStore: CpuSetup | VarOffset: 0x1FB | Size: 0x1
Fast/2: 0x0
Fast/4: 0x1
Fast/8: 0x2
Fast/16: 0x3
System Agent VR Settings
VR Config Enable | VarStore: CpuSetup | VarOffset: 0x108 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
System Agent VR Settings
AC Loadline | VarStore: CpuSetup | VarOffset: 0x10F | Size: 0x2
Min: 0x0 | Max: 0x1869 | Step: 0x0
System Agent VR Settings
DC Loadline | VarStore: CpuSetup | VarOffset: 0x119 | Size: 0x2
Min: 0x0 | Max: 0x1869 | Step: 0x0
System Agent VR Settings
PS Current Threshold1 | VarStore: CpuSetup | VarOffset: 0x123 | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
System Agent VR Settings
PS Current Threshold2 | VarStore: CpuSetup | VarOffset: 0x12D | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
System Agent VR Settings
PS Current Threshold3 | VarStore: CpuSetup | VarOffset: 0x137 | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
System Agent VR Settings
PS3 Enable | VarStore: CpuSetup | VarOffset: 0x13F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
System Agent VR Settings
PS4 Enable | VarStore: CpuSetup | VarOffset: 0x144 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
System Agent VR Settings
IMON Slope | VarStore: CpuSetup | VarOffset: 0x212 | Size: 0x2
Min: 0x0 | Max: 0xC8 | Step: 0x1
System Agent VR Settings
IMON Offset | VarStore: CpuSetup | VarOffset: 0x150 | Size: 0x2
Min: 0x0 | Max: 0xF9FF | Step: 0x1
System Agent VR Settings
IMON Prefix | VarStore: CpuSetup | VarOffset: 0x158 | Size: 0x1
+: 0x0
-: 0x1
System Agent VR Settings
VR Current Limit | VarStore: CpuSetup | VarOffset: 0x15F | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
System Agent VR Settings
VR Voltage Limit | VarStore: CpuSetup | VarOffset: 0x169 | Size: 0x2
Min: 0x0 | Max: 0x1F3F | Step: 0x1
System Agent VR Settings
TDC Enable | VarStore: CpuSetup | VarOffset: 0x17B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
System Agent VR Settings
TDC Current Limit | VarStore: CpuSetup | VarOffset: 0x173 | Size: 0x2
Min: 0x0 | Max: 0x7FFF | Step: 0x1
System Agent VR Settings
TDC Time Window | VarStore: CpuSetup | VarOffset: 0x180 | Size: 0x1
1 ms: 0x1
2 ms: 0x2
3 ms: 0x3
4 ms: 0x4
5 ms: 0x5
6 ms: 0x6
7 ms: 0x7
8 ms: 0x8
10 ms: 0xA
System Agent VR Settings
TDC Lock | VarStore: CpuSetup | VarOffset: 0x185 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Core/IA VR Settings
VR Config Enable | VarStore: CpuSetup | VarOffset: 0x106 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Core/IA VR Settings
AC Loadline | VarStore: CpuSetup | VarOffset: 0x10B | Size: 0x2
Min: 0x0 | Max: 0xF424 | Step: 0x0
Core/IA VR Settings
DC Loadline | VarStore: CpuSetup | VarOffset: 0x115 | Size: 0x2
Min: 0x0 | Max: 0xF424 | Step: 0x0
Core/IA VR Settings
PS Current Threshold1 | VarStore: CpuSetup | VarOffset: 0x11F | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
Core/IA VR Settings
PS Current Threshold2 | VarStore: CpuSetup | VarOffset: 0x129 | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
Core/IA VR Settings
PS Current Threshold3 | VarStore: CpuSetup | VarOffset: 0x133 | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
Core/IA VR Settings
PS3 Enable | VarStore: CpuSetup | VarOffset: 0x13D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Core/IA VR Settings
PS4 Enable | VarStore: CpuSetup | VarOffset: 0x142 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Core/IA VR Settings
IMON Slope | VarStore: CpuSetup | VarOffset: 0x20E | Size: 0x2
Min: 0x0 | Max: 0xC8 | Step: 0x1
Core/IA VR Settings
IMON Offset | VarStore: CpuSetup | VarOffset: 0x14C | Size: 0x2
Min: 0x0 | Max: 0xF9FF | Step: 0x1
Core/IA VR Settings
IMON Prefix | VarStore: CpuSetup | VarOffset: 0x156 | Size: 0x1
+: 0x0
-: 0x1
Core/IA VR Settings
VR Current Limit | VarStore: CpuSetup | VarOffset: 0x15B | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
Core/IA VR Settings
VR Voltage Limit | VarStore: CpuSetup | VarOffset: 0x165 | Size: 0x2
Min: 0x0 | Max: 0x1F3F | Step: 0x1
Core/IA VR Settings
TDC Enable | VarStore: CpuSetup | VarOffset: 0x179 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Core/IA VR Settings
TDC Current Limit | VarStore: CpuSetup | VarOffset: 0x16F | Size: 0x2
Min: 0x0 | Max: 0x7FFF | Step: 0x1
Core/IA VR Settings
TDC Time Window | VarStore: CpuSetup | VarOffset: 0x17E | Size: 0x1
1 ms: 0x1
2 ms: 0x2
3 ms: 0x3
4 ms: 0x4
5 ms: 0x5
6 ms: 0x6
7 ms: 0x7
8 ms: 0x8
10 ms: 0xA
Core/IA VR Settings
TDC Lock | VarStore: CpuSetup | VarOffset: 0x183 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
GT VR Settings
VR Config Enable | VarStore: CpuSetup | VarOffset: 0x107 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
GT VR Settings
AC Loadline | VarStore: CpuSetup | VarOffset: 0x10D | Size: 0x2
Min: 0x0 | Max: 0xF424 | Step: 0x0
GT VR Settings
DC Loadline | VarStore: CpuSetup | VarOffset: 0x117 | Size: 0x2
Min: 0x0 | Max: 0xF424 | Step: 0x0
GT VR Settings
PS Current Threshold1 | VarStore: CpuSetup | VarOffset: 0x121 | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
GT VR Settings
PS Current Threshold2 | VarStore: CpuSetup | VarOffset: 0x12B | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
GT VR Settings
PS Current Threshold3 | VarStore: CpuSetup | VarOffset: 0x135 | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
GT VR Settings
PS3 Enable | VarStore: CpuSetup | VarOffset: 0x13E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
GT VR Settings
PS4 Enable | VarStore: CpuSetup | VarOffset: 0x143 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
GT VR Settings
IMON Slope | VarStore: CpuSetup | VarOffset: 0x210 | Size: 0x2
Min: 0x0 | Max: 0xC8 | Step: 0x1
GT VR Settings
IMON Offset | VarStore: CpuSetup | VarOffset: 0x14E | Size: 0x2
Min: 0x0 | Max: 0xF9FF | Step: 0x1
GT VR Settings
IMON Prefix | VarStore: CpuSetup | VarOffset: 0x157 | Size: 0x1
+: 0x0
-: 0x1
GT VR Settings
VR Current Limit | VarStore: CpuSetup | VarOffset: 0x15D | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
GT VR Settings
VR Voltage Limit | VarStore: CpuSetup | VarOffset: 0x167 | Size: 0x2
Min: 0x0 | Max: 0x1F3F | Step: 0x1
GT VR Settings
TDC Enable | VarStore: CpuSetup | VarOffset: 0x17A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
GT VR Settings
TDC Current Limit | VarStore: CpuSetup | VarOffset: 0x171 | Size: 0x2
Min: 0x0 | Max: 0x7FFF | Step: 0x1
GT VR Settings
TDC Time Window | VarStore: CpuSetup | VarOffset: 0x17F | Size: 0x1
1 ms: 0x1
2 ms: 0x2
3 ms: 0x3
4 ms: 0x4
5 ms: 0x5
6 ms: 0x6
7 ms: 0x7
8 ms: 0x8
10 ms: 0xA
GT VR Settings
TDC Lock | VarStore: CpuSetup | VarOffset: 0x184 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
VccIn VR Settings
VR Config Enable | VarStore: CpuSetup | VarOffset: 0x10A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
VccIn VR Settings
AC Loadline | VarStore: CpuSetup | VarOffset: 0x113 | Size: 0x2
Min: 0x0 | Max: 0xF424 | Step: 0x0
VccIn VR Settings
DC Loadline | VarStore: CpuSetup | VarOffset: 0x11D | Size: 0x2
Min: 0x0 | Max: 0xF424 | Step: 0x0
VccIn VR Settings
PS Current Threshold1 | VarStore: CpuSetup | VarOffset: 0x127 | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
VccIn VR Settings
PS Current Threshold2 | VarStore: CpuSetup | VarOffset: 0x131 | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
VccIn VR Settings
PS Current Threshold3 | VarStore: CpuSetup | VarOffset: 0x13B | Size: 0x2
Min: 0x0 | Max: 0x200 | Step: 0x1
VccIn VR Settings
PS3 Enable | VarStore: CpuSetup | VarOffset: 0x141 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
VccIn VR Settings
PS4 Enable | VarStore: CpuSetup | VarOffset: 0x146 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
VccIn VR Settings
IMON Slope | VarStore: CpuSetup | VarOffset: 0x216 | Size: 0x2
Min: 0x0 | Max: 0xC8 | Step: 0x1
VccIn VR Settings
IMON Offset | VarStore: CpuSetup | VarOffset: 0x154 | Size: 0x2
Min: 0x0 | Max: 0xF9FF | Step: 0x1
VccIn VR Settings
IMON Prefix | VarStore: CpuSetup | VarOffset: 0x15A | Size: 0x1
+: 0x0
-: 0x1
VccIn VR Settings
VR Current Limit | VarStore: CpuSetup | VarOffset: 0x163 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
VccIn VR Settings
VR Voltage Limit | VarStore: CpuSetup | VarOffset: 0x16D | Size: 0x2
Min: 0x0 | Max: 0x1F3F | Step: 0x1
VccIn VR Settings
TDC Enable | VarStore: CpuSetup | VarOffset: 0x17D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
VccIn VR Settings
TDC Current Limit | VarStore: CpuSetup | VarOffset: 0x177 | Size: 0x2
Min: 0x0 | Max: 0x7FFF | Step: 0x1
VccIn VR Settings
TDC Time Window | VarStore: CpuSetup | VarOffset: 0x182 | Size: 0x1
1 ms: 0x1
2 ms: 0x2
3 ms: 0x3
4 ms: 0x4
5 ms: 0x5
6 ms: 0x6
7 ms: 0x7
8 ms: 0x8
10 ms: 0xA
VccIn VR Settings
TDC Lock | VarStore: CpuSetup | VarOffset: 0x187 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
RFI Settings
RFI Frequency Adjustment | VarStore: CpuSetup | VarOffset: 0x1ED | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x0
RFI Settings
RFI Frequency Prefix | VarStore: CpuSetup | VarOffset: 0x1EE | Size: 0x1
+: 0x0
-: 0x1
RFI Settings
RFI Spread Spectrum | VarStore: CpuSetup | VarOffset: 0x1EF | Size: 0x1
0.5%: 0x1
1%: 0x2
1.5%: 0x3
2%: 0x4
3%: 0x5
4%: 0x6
5%: 0x7
6%: 0x8
RFI Settings
RFI Frequency | VarStore: CpuSetup | VarOffset: 0x1F0 | Size: 0x2
Min: 0x0 | Max: 0x77E | Step: 0x0
RFI Settings
RFI Spread Spectrum | VarStore: CpuSetup | VarOffset: 0x1F2 | Size: 0x1
Min: 0x0 | Max: 0x64 | Step: 0x0
Power Limit 3 Settings
Power Limit 3 Override | VarStore: CpuSetup | VarOffset: 0x1D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Power Limit 3 Settings
Power Limit 3 | VarStore: CpuSetup | VarOffset: 0x1E | Size: 0x4
Min: 0x0 | Max: 0x3E7F83 | Step: 0x7D
Power Limit 3 Settings
Power Limit 3 Time Window | VarStore: CpuSetup | VarOffset: 0x22 | Size: 0x1
0: 0x0
3: 0x3
4: 0x4
5: 0x5
6: 0x6
7: 0x7
8: 0x8
10: 0xA
12: 0xC
14: 0xE
16: 0x10
20: 0x14
24: 0x18
28: 0x1C
32: 0x20
40: 0x28
48: 0x30
56: 0x38
64: 0x40
Power Limit 3 Settings
Power Limit 3 Duty Cycle | VarStore: CpuSetup | VarOffset: 0x23 | Size: 0x1
Min: 0x0 | Max: 0x64 | Step: 0x0
Power Limit 3 Settings
Power Limit 3 Lock | VarStore: CpuSetup | VarOffset: 0x24 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Config TDP Configurations
Configurable TDP Boot Mode | VarStore: CpuSetup | VarOffset: 0x3F | Size: 0x1
Nominal: 0x0
Down: 0x1
Up: 0x2
Deactivate: 0xFF
Config TDP Configurations
Configurable TDP Lock | VarStore: CpuSetup | VarOffset: 0x40 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Config TDP Configurations
CTDP BIOS control | VarStore: CpuSetup | VarOffset: 0x41 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Config TDP Configurations
Power Limit 1 | VarStore: CpuSetup | VarOffset: 0x56 | Size: 0x4
Min: 0x0 | Max: 0x3E7F83 | Step: 0x7D
Config TDP Configurations
Power Limit 2 | VarStore: CpuSetup | VarOffset: 0x5A | Size: 0x4
Min: 0x0 | Max: 0x3E7F83 | Step: 0x7D
Config TDP Configurations
Power Limit 1 Time Window | VarStore: CpuSetup | VarOffset: 0x5E | Size: 0x1
0: 0x0
1: 0x1
2: 0x2
3: 0x3
4: 0x4
5: 0x5
6: 0x6
7: 0x7
8: 0x8
10: 0xA
12: 0xC
14: 0xE
16: 0x10
20: 0x14
24: 0x18
28: 0x1C
32: 0x20
40: 0x28
48: 0x30
56: 0x38
64: 0x40
80: 0x50
96: 0x60
112: 0x70
128: 0x80
Config TDP Configurations
ConfigTDP Turbo Activation Ratio | VarStore: CpuSetup | VarOffset: 0x5F | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Config TDP Configurations
Power Limit 1 | VarStore: CpuSetup | VarOffset: 0x60 | Size: 0x4
Min: 0x0 | Max: 0x3E7F83 | Step: 0x7D
Config TDP Configurations
Power Limit 2 | VarStore: CpuSetup | VarOffset: 0x64 | Size: 0x4
Min: 0x0 | Max: 0x3E7F83 | Step: 0x7D
Config TDP Configurations
Power Limit 1 Time Window | VarStore: CpuSetup | VarOffset: 0x68 | Size: 0x1
0: 0x0
1: 0x1
2: 0x2
3: 0x3
4: 0x4
5: 0x5
6: 0x6
7: 0x7
8: 0x8
10: 0xA
12: 0xC
14: 0xE
16: 0x10
20: 0x14
24: 0x18
28: 0x1C
32: 0x20
40: 0x28
48: 0x30
56: 0x38
64: 0x40
80: 0x50
96: 0x60
112: 0x70
128: 0x80
Config TDP Configurations
ConfigTDP Turbo Activation Ratio | VarStore: CpuSetup | VarOffset: 0x69 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Config TDP Configurations
Power Limit 1 | VarStore: CpuSetup | VarOffset: 0x6A | Size: 0x4
Min: 0x0 | Max: 0x3E7F83 | Step: 0x7D
Config TDP Configurations
Power Limit 2 | VarStore: CpuSetup | VarOffset: 0x6E | Size: 0x4
Min: 0x0 | Max: 0x3E7F83 | Step: 0x7D
Config TDP Configurations
Power Limit 1 Time Window | VarStore: CpuSetup | VarOffset: 0x72 | Size: 0x1
0: 0x0
1: 0x1
2: 0x2
3: 0x3
4: 0x4
5: 0x5
6: 0x6
7: 0x7
8: 0x8
10: 0xA
12: 0xC
14: 0xE
16: 0x10
20: 0x14
24: 0x18
28: 0x1C
32: 0x20
40: 0x28
48: 0x30
56: 0x38
64: 0x40
80: 0x50
96: 0x60
112: 0x70
128: 0x80
Config TDP Configurations
ConfigTDP Turbo Activation Ratio | VarStore: CpuSetup | VarOffset: 0x73 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
View/Configure CPU Lock Options
CFG Lock | VarStore: CpuSetup | VarOffset: 0x3E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
View/Configure CPU Lock Options
Overclocking Lock | VarStore: CpuSetup | VarOffset: 0xDA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-FW Configuration
ME State | VarStore: MeSetupStorage | VarOffset: 0x2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-FW Configuration
Manageability Features State | VarStore: MeSetupStorage | VarOffset: 0x0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-FW Configuration
AMT BIOS Features | VarStore: MeSetup | VarOffset: 0x17 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-FW Configuration
ME Unconfig on RTC Clear | VarStore: MeSetup | VarOffset: 0x12 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-FW Configuration
Comms Hub Support | VarStore: MeSetup | VarOffset: 0x6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-FW Configuration
JHI Support | VarStore: MeSetup | VarOffset: 0x16 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-FW Configuration
Extend CSME Measurement to TPM-PCR | VarStore: MeSetup | VarOffset: 0x2C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-FW Configuration
Core Bios Done Message | VarStore: MeSetup | VarOffset: 0x13 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PTT Configuration
TPM Device Selection | VarStore: MeSetup | VarOffset: 0x37 | Size: 0x1
dTPM: 0x0
PTT: 0x1
PTT Configuration
TPM 1.2 Deactivate | VarStore: MeSetupStorage | VarOffset: 0x6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Firmware Update Configuration
ME FW Image Re-Flash | VarStore: MeSetup | VarOffset: 0x5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Firmware Update Configuration
FW Update | VarStore: MeSetupStorage | VarOffset: 0x1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ME Debug Configuration
HECI Timeouts | VarStore: MeSetup | VarOffset: 0x7
ME Debug Configuration
Force ME DID Init Status | VarStore: MeSetup | VarOffset: 0x8 | Size: 0x1
Disabled: 0x0
0 - Success: 0x1
1 - No Memory in Channels: 0x2
2 - Memory Init Error: 0x3
ME Debug Configuration
CPU Replaced Polling Disable | VarStore: MeSetup | VarOffset: 0x9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ME Debug Configuration
ME DID Message | VarStore: MeSetup | VarOffset: 0xA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ME Debug Configuration
HECI Message check Disable | VarStore: MeSetup | VarOffset: 0xB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ME Debug Configuration
MBP HOB Skip | VarStore: MeSetup | VarOffset: 0xC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ME Debug Configuration
HECI2 Interface Communication | VarStore: MeSetup | VarOffset: 0xD
ME Debug Configuration
KT Device | VarStore: MeSetup | VarOffset: 0xE
ME Debug Configuration
End Of Post Message | VarStore: MeSetup | VarOffset: 0x14 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ME Debug Configuration
D0I3 Setting for HECI Disable | VarStore: MeSetup | VarOffset: 0xF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ME Debug Configuration
MCTP Broadcast Cycle | VarStore: MeSetup | VarOffset: 0x10 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
FIPS Mode
FIPS Mode Select | VarStore: MeSetupStorage | VarOffset: 0xB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Anti-Rollback SVN Configuration
Automatic HW-Enforced Anti-Rollback SVN | VarStore: MeSetup | VarOffset: 0x2B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Anti-Rollback SVN Configuration
Set HW-Enforced Anti-Rollback for Current SVN | VarStore: MeSetupStorage | VarOffset: 0xC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Cpu Thermal Configuration
DTS SMM | VarStore: CpuSetup | VarOffset: 0x1B6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Critical Temp Reporting (Out Of spec): 0x2
Cpu Thermal Configuration
Tcc Activation Offset | VarStore: CpuSetup | VarOffset: 0x7A | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x0
Cpu Thermal Configuration
Tcc Offset Time Window | VarStore: CpuSetup | VarOffset: 0x188 | Size: 0x4
Disabled: 0x0
5 ms: 0x5
10 ms: 0xA
55 ms: 0x37
156 ms: 0x9C
375 ms: 0x177
500 ms: 0x1F4
750 ms: 0x2EE
1 sec: 0x3E8
2 sec: 0x7D0
3 sec: 0xBB8
4 sec: 0xFA0
5 sec: 0x1388
6 sec: 0x1770
7 sec: 0x1B58
8 sec: 0x1F40
10 sec: 0x2710
12 sec: 0x2EE0
14 sec: 0x36B0
16 sec: 0x3E80
20 sec: 0x4E20
24 sec: 0x5DC0
28 sec: 0x6D60
32 sec: 0x7D00
40 sec: 0x9C40
48 sec: 0xBB80
56 sec: 0xDAC0
64 sec: 0xFA00
80 sec: 0x13880
96 sec: 0x17700
112 sec: 0x1B580
128 sec: 0x1F400
160 sec: 0x27100
192 sec: 0x2EE00
224 sec: 0x36B00
256 sec: 0x3E800
320 sec: 0x4E200
384 sec: 0x5DC00
448 sec: 0x6D600
Cpu Thermal Configuration
Tcc Offset Clamp Enable | VarStore: CpuSetup | VarOffset: 0x18C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Cpu Thermal Configuration
Tcc Offset Lock Enable | VarStore: CpuSetup | VarOffset: 0x18D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Cpu Thermal Configuration
Bi-directional PROCHOT# | VarStore: CpuSetup | VarOffset: 0x75 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Cpu Thermal Configuration
Disable PROCHOT# Output | VarStore: CpuSetup | VarOffset: 0x76 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Cpu Thermal Configuration
Disable VR Thermal Alert | VarStore: CpuSetup | VarOffset: 0x77 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Cpu Thermal Configuration
PROCHOT Response | VarStore: CpuSetup | VarOffset: 0x79 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Cpu Thermal Configuration
PROCHOT Lock | VarStore: CpuSetup | VarOffset: 0x78 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Cpu Thermal Configuration
ACPI T-States | VarStore: CpuSetup | VarOffset: 0x74
Cpu Thermal Configuration
PECI Reset | VarStore: CpuSetup | VarOffset: 0x236 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Cpu Thermal Configuration
PECI C10 Reset | VarStore: CpuSetup | VarOffset: 0x235 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Thermal Configuration
Automatic Thermal Reporting | VarStore: CpuSetup | VarOffset: 0x1E6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Thermal Configuration
Critical Trip Point | VarStore: Setup | VarOffset: 0x3B2 | Size: 0x1
15 C: 0xF
23 C: 0x17
31 C: 0x1F
39 C: 0x27
47 C: 0x2F
55 C: 0x37
63 C: 0x3F
71 C: 0x47
79 C: 0x4F
87 C: 0x57
95 C: 0x5F
100 C: 0x64
103 C: 0x67
111 C: 0x6F
119 C (POR): 0x77
127 C: 0x7F
Platform Thermal Configuration
Active Trip Point 0 | VarStore: Setup | VarOffset: 0x3AE | Size: 0x1
Disabled: 0x7F
15 C: 0xF
23 C: 0x17
31 C: 0x1F
39 C: 0x27
47 C: 0x2F
55 C: 0x37
63 C: 0x3F
71 C: 0x47
79 C: 0x4F
87 C: 0x57
95 C: 0x5F
103 C: 0x67
111 C: 0x6F
119 C (POR): 0x77
Platform Thermal Configuration
Active Trip Point 0 Fan Speed | VarStore: Setup | VarOffset: 0x3B0 | Size: 0x1
Min: 0x0 | Max: 0x64 | Step: 0x1
Platform Thermal Configuration
Active Trip Point 1 | VarStore: Setup | VarOffset: 0x3AD | Size: 0x1
Disabled: 0x7F
15 C: 0xF
23 C: 0x17
31 C: 0x1F
39 C: 0x27
47 C: 0x2F
55 C: 0x37
63 C: 0x3F
71 C: 0x47
79 C: 0x4F
87 C: 0x57
95 C: 0x5F
103 C: 0x67
111 C: 0x6F
119 C (POR): 0x77
Platform Thermal Configuration
Active Trip Point 1 Fan Speed | VarStore: Setup | VarOffset: 0x3AF | Size: 0x1
Min: 0x0 | Max: 0x64 | Step: 0x1
Platform Thermal Configuration
Passive Trip Point | VarStore: Setup | VarOffset: 0x3B1 | Size: 0x1
Disabled: 0x7F
15 C: 0xF
23 C: 0x17
31 C: 0x1F
39 C: 0x27
47 C: 0x2F
55 C: 0x37
63 C: 0x3F
71 C: 0x47
79 C: 0x4F
87 C: 0x57
95 C: 0x5F
103 C: 0x67
111 C: 0x6F
119 C (POR): 0x77
Platform Thermal Configuration
Passive TC1 Value | VarStore: Setup | VarOffset: 0x3B3 | Size: 0x1
Min: 0x1 | Max: 0x10 | Step: 0x1
Platform Thermal Configuration
Passive TC2 Value | VarStore: Setup | VarOffset: 0x3B4 | Size: 0x1
Min: 0x1 | Max: 0x10 | Step: 0x1
Platform Thermal Configuration
Passive TSP Value | VarStore: Setup | VarOffset: 0x3B5 | Size: 0x1
Min: 0x2 | Max: 0x20 | Step: 0x2
Platform Thermal Configuration
Active Trip Points | VarStore: Setup | VarOffset: 0x3B6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Thermal Configuration
Passive Trip Points | VarStore: Setup | VarOffset: 0x3B7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Thermal Configuration
Critical Trip Points | VarStore: Setup | VarOffset: 0x3B8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Thermal Configuration
PCH Temp Read | VarStore: Setup | VarOffset: 0x3BE
Platform Thermal Configuration
CPU Energy Read | VarStore: Setup | VarOffset: 0x3BD
Platform Thermal Configuration
CPU Temp Read | VarStore: Setup | VarOffset: 0x3BC
Platform Thermal Configuration
Alert Enable Lock | VarStore: Setup | VarOffset: 0x3BF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Thermal Configuration
PCH Alert | VarStore: Setup | VarOffset: 0x3C0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Thermal Configuration
DIMM Alert | VarStore: Setup | VarOffset: 0x3C1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Thermal Configuration
CPU Temp | VarStore: Setup | VarOffset: 0x3C2 | Size: 0x1
Min: 0x1 | Max: 0x6E | Step: 0x1
Platform Thermal Configuration
CPU Fan Speed | VarStore: Setup | VarOffset: 0x3C3 | Size: 0x1
Min: 0x1 | Max: 0x64 | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Intel(R) Dynamic Tuning | VarStore: Setup | VarOffset: 0x3C4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Configuration
Processor Thermal Device | VarStore: Setup | VarOffset: 0x3C6 | Size: 0x1
Disabled: 0x0
SA Thermal Device: 0x1
Intel(R) Dynamic Tuning Configuration
Active Thermal Trip Point | VarStore: Setup | VarOffset: 0x3C7 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Passive Thermal Trip Point | VarStore: Setup | VarOffset: 0x3C8 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Critical Thermal Trip Point | VarStore: Setup | VarOffset: 0x3C9 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
S3/CS Thermal Trip Point | VarStore: Setup | VarOffset: 0x3CA | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Hot Thermal Trip Point | VarStore: Setup | VarOffset: 0x3CC | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Thermal Sampling Period | VarStore: Setup | VarOffset: 0x3CB | Size: 0x1
Min: 0x0 | Max: 0x64 | Step: 0x1
Intel(R) Dynamic Tuning Configuration
PPCC Step Size | VarStore: Setup | VarOffset: 0x3CD | Size: 0x4
0.5 Watts: 0x1F4
1.0 Watts: 0x3E8
1.5 Watts: 0x5DC
2.0 Watts: 0x7D0
Intel(R) Dynamic Tuning Configuration
Minimum Power Limit (cTDP Nom) | VarStore: Setup | VarOffset: 0x3D6 | Size: 0x2
Min: 0x0 | Max: 0x7530 | Step: 0x7D
Intel(R) Dynamic Tuning Configuration
Minimum Power Limit (cTDP Down) | VarStore: Setup | VarOffset: 0x3D8 | Size: 0x2
Min: 0x0 | Max: 0x7530 | Step: 0x7D
Intel(R) Dynamic Tuning Configuration
Minimum Power Limit (cTDP up) | VarStore: Setup | VarOffset: 0x3DA | Size: 0x2
Min: 0x0 | Max: 0x7530 | Step: 0x7D
Intel(R) Dynamic Tuning Configuration
CLPO Enable | VarStore: Setup | VarOffset: 0x3D1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Configuration
CLPO Start PState | VarStore: Setup | VarOffset: 0x3D2 | Size: 0x1
Min: 0x0 | Max: 0x10 | Step: 0x1
Intel(R) Dynamic Tuning Configuration
CLPO Step Size | VarStore: Setup | VarOffset: 0x3D3 | Size: 0x1
Min: 0x0 | Max: 0x64 | Step: 0x1
Intel(R) Dynamic Tuning Configuration
CLPO Power Control | VarStore: Setup | VarOffset: 0x3D4 | Size: 0x1
Disabled: 0x0
SMT Off lining: 0x1
Core Off lining: 0x2
Intel(R) Dynamic Tuning Configuration
CLPO Performance Control | VarStore: Setup | VarOffset: 0x3D5 | Size: 0x1
Disabled: 0x0
SMT Off lining: 0x1
Core Off lining: 0x2
Intel(R) Dynamic Tuning Configuration
ConfigTDP | VarStore: Setup | VarOffset: 0x3DC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Configuration
Intel(R) Dynamic Tuning Configuration | VarStore: Setup | VarOffset: 0x3C5 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Intel(R) Dynamic Tuning Configuration
FAN1 Device | VarStore: Setup | VarOffset: 0x3DD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Configuration
FAN2 Device | VarStore: Setup | VarOffset: 0x698 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Configuration
FAN3 Device | VarStore: Setup | VarOffset: 0x699 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Configuration
Display participant | VarStore: Setup | VarOffset: 0x3DE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Configuration
Display Low Limit | VarStore: Setup | VarOffset: 0x3E0 | Size: 0x1
Min: 0x0 | Max: 0x64 | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Display High Limit | VarStore: Setup | VarOffset: 0x3DF | Size: 0x1
Min: 0x0 | Max: 0x64 | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Wireless participant | VarStore: Setup | VarOffset: 0x3E1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Configuration
Active Thermal Trip Point | VarStore: Setup | VarOffset: 0x3E2 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Passive Thermal Trip Point | VarStore: Setup | VarOffset: 0x3E3 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Critical Thermal Trip Point | VarStore: Setup | VarOffset: 0x3E4 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
S3/CS Thermal Trip Point | VarStore: Setup | VarOffset: 0x3E5 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Hot Thermal Trip Point | VarStore: Setup | VarOffset: 0x3E6 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Thermal Sampling Period | VarStore: Setup | VarOffset: 0x3E7 | Size: 0x1
Min: 0x0 | Max: 0x64 | Step: 0x1
Intel(R) Dynamic Tuning Configuration
WWAN participant | VarStore: Setup | VarOffset: 0x3E8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Configuration
Active Thermal Trip Point | VarStore: Setup | VarOffset: 0x3E9 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Passive Thermal Trip Point | VarStore: Setup | VarOffset: 0x3EA | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Critical Thermal Trip Point | VarStore: Setup | VarOffset: 0x3EB | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
S3/CS Thermal Trip Point | VarStore: Setup | VarOffset: 0x3EC | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Hot Thermal Trip Point | VarStore: Setup | VarOffset: 0x3ED | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Charger participant | VarStore: Setup | VarOffset: 0x3EE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Configuration
Power participant | VarStore: Setup | VarOffset: 0x3EF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Configuration
2D Camera participant | VarStore: Setup | VarOffset: 0x3F2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Configuration
Battery Participant | VarStore: Setup | VarOffset: 0x679 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Configuration
Intel Dynamic Tuning Battery Sampling Period | VarStore: Setup | VarOffset: 0x3F0 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Storage participant1 | VarStore: Setup | VarOffset: 0x3F3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Configuration
Active Thermal Trip Point | VarStore: Setup | VarOffset: 0x3F4 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Passive Thermal Trip Point | VarStore: Setup | VarOffset: 0x3F5 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Critical Thermal Trip Point | VarStore: Setup | VarOffset: 0x3F6 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
S3/CS Thermal Trip Point | VarStore: Setup | VarOffset: 0x3F7 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Hot Thermal Trip Point | VarStore: Setup | VarOffset: 0x3F8 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Storage participant2 | VarStore: Setup | VarOffset: 0x3F9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Configuration
Active Thermal Trip Point | VarStore: Setup | VarOffset: 0x3FA | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Passive Thermal Trip Point | VarStore: Setup | VarOffset: 0x3FB | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Critical Thermal Trip Point | VarStore: Setup | VarOffset: 0x3FC | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
S3/CS Thermal Trip Point | VarStore: Setup | VarOffset: 0x3FD | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Hot Thermal Trip Point | VarStore: Setup | VarOffset: 0x3FE | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Virtual Sensor participant 1 | VarStore: Setup | VarOffset: 0x3FF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Configuration
Active Thermal Trip Point | VarStore: Setup | VarOffset: 0x400 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Passive Thermal Trip Point | VarStore: Setup | VarOffset: 0x401 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Critical Thermal Trip Point | VarStore: Setup | VarOffset: 0x402 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Hot Thermal Trip Point | VarStore: Setup | VarOffset: 0x404 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
S3/CS Thermal Trip Point | VarStore: Setup | VarOffset: 0x403 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Virtual Sensor participant 2 | VarStore: Setup | VarOffset: 0x405 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Configuration
Active Thermal Trip Point | VarStore: Setup | VarOffset: 0x406 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Passive Thermal Trip Point | VarStore: Setup | VarOffset: 0x407 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Critical Thermal Trip Point | VarStore: Setup | VarOffset: 0x408 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Hot Thermal Trip Point | VarStore: Setup | VarOffset: 0x40A | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
S3/CS Thermal Trip Point | VarStore: Setup | VarOffset: 0x409 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Sensor Device 1 | VarStore: Setup | VarOffset: 0x40C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Configuration
Active Thermal Trip Point | VarStore: Setup | VarOffset: 0x40D | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Passive Thermal Trip Point | VarStore: Setup | VarOffset: 0x40E | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Critical Thermal Trip Point | VarStore: Setup | VarOffset: 0x40F | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
S3/CS Thermal Trip Point | VarStore: Setup | VarOffset: 0x410 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Hot Thermal Trip Point | VarStore: Setup | VarOffset: 0x411 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Thermal Sampling Period | VarStore: Setup | VarOffset: 0x412 | Size: 0x1
Min: 0x0 | Max: 0x64 | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Sensor Device 2 | VarStore: Setup | VarOffset: 0x413 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Configuration
Active Thermal Trip Point | VarStore: Setup | VarOffset: 0x414 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Passive Thermal Trip Point | VarStore: Setup | VarOffset: 0x415 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Critical Thermal Trip Point | VarStore: Setup | VarOffset: 0x416 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
S3/CS Thermal Trip Point | VarStore: Setup | VarOffset: 0x417 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Hot Thermal Trip Point | VarStore: Setup | VarOffset: 0x418 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Thermal Sampling Period | VarStore: Setup | VarOffset: 0x419 | Size: 0x1
Min: 0x0 | Max: 0x64 | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Sensor Device 3 | VarStore: Setup | VarOffset: 0x41A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Configuration
Active Thermal Trip Point | VarStore: Setup | VarOffset: 0x41B | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Passive Thermal Trip Point | VarStore: Setup | VarOffset: 0x41C | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Critical Thermal Trip Point | VarStore: Setup | VarOffset: 0x41D | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
S3/CS Thermal Trip Point | VarStore: Setup | VarOffset: 0x41E | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Hot Thermal Trip Point | VarStore: Setup | VarOffset: 0x41F | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Thermal Sampling Period | VarStore: Setup | VarOffset: 0x420 | Size: 0x1
Min: 0x0 | Max: 0x64 | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Sensor Device 4 | VarStore: Setup | VarOffset: 0x421 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Configuration
Active Thermal Trip Point | VarStore: Setup | VarOffset: 0x422 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Passive Thermal Trip Point | VarStore: Setup | VarOffset: 0x423 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Critical Thermal Trip Point | VarStore: Setup | VarOffset: 0x424 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
S3/CS Thermal Trip Point | VarStore: Setup | VarOffset: 0x425 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Hot Thermal Trip Point | VarStore: Setup | VarOffset: 0x426 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Thermal Sampling Period | VarStore: Setup | VarOffset: 0x427 | Size: 0x1
Min: 0x0 | Max: 0x64 | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Sensor Device 5 | VarStore: Setup | VarOffset: 0x428 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Configuration
Active Thermal Trip Point | VarStore: Setup | VarOffset: 0x429 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Passive Thermal Trip Point | VarStore: Setup | VarOffset: 0x42A | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Critical Thermal Trip Point | VarStore: Setup | VarOffset: 0x42B | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
S3/CS Thermal Trip Point | VarStore: Setup | VarOffset: 0x42C | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Hot Thermal Trip Point | VarStore: Setup | VarOffset: 0x42D | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Thermal Sampling Period | VarStore: Setup | VarOffset: 0x42E | Size: 0x1
Min: 0x0 | Max: 0x64 | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Discret Graphics Sensor Device | VarStore: Setup | VarOffset: 0x69A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Dynamic Tuning Configuration
Active Thermal Trip Point | VarStore: Setup | VarOffset: 0x69B | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Passive Thermal Trip Point | VarStore: Setup | VarOffset: 0x69C | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Critical Thermal Trip Point | VarStore: Setup | VarOffset: 0x69D | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
S3/CS Thermal Trip Point | VarStore: Setup | VarOffset: 0x69E | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Hot Thermal Trip Point | VarStore: Setup | VarOffset: 0x69F | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Intel(R) Dynamic Tuning Configuration
Thermal Sampling Period | VarStore: Setup | VarOffset: 0x6A0 | Size: 0x1
Min: 0x0 | Max: 0x64 | Step: 0x1
OEM variable and Object
Design Variable 0 | VarStore: Setup | VarOffset: 0x43C | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
OEM variable and Object
Design Variable 1 | VarStore: Setup | VarOffset: 0x43D | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
OEM variable and Object
Design Variable 2 | VarStore: Setup | VarOffset: 0x43E | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
OEM variable and Object
Design Variable 3 | VarStore: Setup | VarOffset: 0x43F | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
OEM variable and Object
Design Variable 4 | VarStore: Setup | VarOffset: 0x440 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
OEM variable and Object
Design Variable 5 | VarStore: Setup | VarOffset: 0x441 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
OEM variable and Object
PPCC Object | VarStore: Setup | VarOffset: 0x42F | Size: 0x1
Disabled: 0x1
Enabled: 0x0
OEM variable and Object
PDRT Object | VarStore: Setup | VarOffset: 0x430 | Size: 0x1
Disabled: 0x1
Enabled: 0x0
OEM variable and Object
ARTG Object | VarStore: Setup | VarOffset: 0x431 | Size: 0x1
Disabled: 0x1
Enabled: 0x0
OEM variable and Object
PMAX Object | VarStore: Setup | VarOffset: 0x432 | Size: 0x1
Disabled: 0x1
Enabled: 0x0
OEM variable and Object
_TMP 1 Object | VarStore: Setup | VarOffset: 0x433 | Size: 0x1
Disabled: 0x1
Enabled: 0x0
OEM variable and Object
_TMP 2 Object | VarStore: Setup | VarOffset: 0x434 | Size: 0x1
Disabled: 0x1
Enabled: 0x0
OEM variable and Object
_TMP 3 Object | VarStore: Setup | VarOffset: 0x435 | Size: 0x1
Disabled: 0x1
Enabled: 0x0
OEM variable and Object
_TMP 4 Object | VarStore: Setup | VarOffset: 0x436 | Size: 0x1
Disabled: 0x1
Enabled: 0x0
OEM variable and Object
_TMP 5 Object | VarStore: Setup | VarOffset: 0x437 | Size: 0x1
Disabled: 0x1
Enabled: 0x0
OEM variable and Object
_TMP 6 Object | VarStore: Setup | VarOffset: 0x438 | Size: 0x1
Disabled: 0x1
Enabled: 0x0
OEM variable and Object
_TMP 7 Object | VarStore: Setup | VarOffset: 0x439 | Size: 0x1
Disabled: 0x1
Enabled: 0x0
OEM variable and Object
_TMP 8 Object | VarStore: Setup | VarOffset: 0x43A | Size: 0x1
Disabled: 0x1
Enabled: 0x0
OEM variable and Object
Optional Objects | VarStore: Setup | VarOffset: 0x43B | Size: 0x1
Disabled: 0x1
Enabled: 0x0
Platform Settings
Secondary Configuration Rework Option | VarStore: Setup | VarOffset: 0x692 | Size: 0x1
Disabled: 0x0
x4 PCIe Slot: 0x1
TBT AIC: 0x2
Platform Settings
Secondary Configuration Rework Option For TBT | VarStore: Setup | VarOffset: 0x692 | Size: 0x1
TBT BP Onboard Enable: 0x0
TBT FP AIC Enable: 0x1
Platform Settings
UCSI Retry Mechanism | VarStore: Setup | VarOffset: 0x54F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Settings
PS2 Keyboard and Mouse | VarStore: Setup | VarOffset: 0x3AB | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Platform Settings
Power Loss Notification Feature | VarStore: Setup | VarOffset: 0x68B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Settings
Charging Method | VarStore: Setup | VarOffset: 0x50F | Size: 0x1
Normal Charging: 0x0
Fast Charging: 0x1
Platform Settings
Pmic Vcc IO Level | VarStore: Setup | VarOffset: 0x3B9 | Size: 0x1
Disabled: 0x7
1.05V: 0x0
1.071V: 0x1
1.023V: 0x2
0.997V: 0x3
0.850V: 0x4
0.900V: 0x5
0.950V: 0x6
Platform Settings
Pmic Vddq Level | VarStore: Setup | VarOffset: 0x3BA | Size: 0x1
Disabled: 0x8
0: 0x0
1: 0x1
2: 0x2
3: 0x3
4: 0x4
5: 0x5
6: 0x6
7: 0x7
Platform Settings
Pmic SlpS0 VM Support | VarStore: Setup | VarOffset: 0x500 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Settings
Enable FFU Support | VarStore: Setup | VarOffset: 0x4B6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Settings
Delay to wait for WWAN device to be ready before SAR reset. | VarStore: Setup | VarOffset: 0x505 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Platform Settings
Type-C BSSB Mode | VarStore: Setup | VarOffset: 0x507 | Size: 0x1
Mode 0: 0x0
Mode 1: 0x1
Platform Settings
Enable PowerMeter | VarStore: Setup | VarOffset: 0x545 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Settings
HID Event Filter Driver | VarStore: Setup | VarOffset: 0x4FF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Settings
HEBC value | VarStore: Setup | VarOffset: 0x501 | Size: 0x4
Min: 0x0 | Max: 0xFFFFFFFF | Step: 0x1
Platform Settings
Pcie Slot 1 to x4 Mode Rework | VarStore: Setup | VarOffset: 0x541 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Platform Settings
PCIe x16 slot GSPI0_CLK Rework | VarStore: Setup | VarOffset: 0x54D | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Platform Settings
PCIe x16 slot GSXDOUT Rework | VarStore: Setup | VarOffset: 0x54E | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Platform Settings
DGPU Power Enable | VarStore: Setup | VarOffset: 0x543 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Platform Settings
System Time and Alarm Source | VarStore: Setup | VarOffset: 0x551 | Size: 0x1
ACPI Time and Alarm Device: 0x0
Legacy RTC: 0x1
Platform Settings
Intel Trusted Device Setup Boot | VarStore: Setup | VarOffset: 0x68A | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Platform Settings
Support PEG Bifurcation Card | VarStore: Setup | VarOffset: 0x697 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
ACPI D3Cold settings
ACPI D3Cold Support | VarStore: Setup | VarOffset: 0x442 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
VR Ramp up delay | VarStore: Setup | VarOffset: 0x44E | Size: 0x2
Min: 0x0 | Max: 0x64 | Step: 0x10
ACPI D3Cold settings
PCIE Slot 5 Device Power-on delay in ms | VarStore: Setup | VarOffset: 0x443 | Size: 0x1
Min: 0x0 | Max: 0x64 | Step: 0x14
ACPI D3Cold settings
Audio Delay | VarStore: Setup | VarOffset: 0x446 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x14
ACPI D3Cold settings
SensorHub | VarStore: Setup | VarOffset: 0x44C | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x14
ACPI D3Cold settings
TouchPad | VarStore: Setup | VarOffset: 0x448 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x14
ACPI D3Cold settings
TouchPanel | VarStore: Setup | VarOffset: 0x44A | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x14
ACPI D3Cold settings
P-state Capping | VarStore: Setup | VarOffset: 0x450 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
USB Port 1 | VarStore: Setup | VarOffset: 0x444 | Size: 0x1
High Speed: 0x1
Super Speed: 0x2
Disabled: 0x0
ACPI D3Cold settings
USB Port 2 | VarStore: Setup | VarOffset: 0x445 | Size: 0x1
Disabled: 0x0
High Speed: 0x1
Super Speed: 0x2
Super Speed WWAN: 0x4
ACPI D3Cold settings
ZPODD | VarStore: Setup | VarOffset: 0x452 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
WWAN | VarStore: Setup | VarOffset: 0x453 | Size: 0x1
Disabled: 0x0
D0/L1.2: 0x1
D3/L2: 0x3
ACPI D3Cold settings
Bluetooth | VarStore: Setup | VarOffset: 0x693 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
DG1 | VarStore: Setup | VarOffset: 0x696 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
Sata Port 0 | VarStore: Setup | VarOffset: 0x454 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
Sata Port 1 | VarStore: Setup | VarOffset: 0x455 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
Sata Port 2 | VarStore: Setup | VarOffset: 0x456 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
Sata Port 3 | VarStore: Setup | VarOffset: 0x457 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
Sata Port 4 | VarStore: Setup | VarOffset: 0x458 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
Sata Port 5 | VarStore: Setup | VarOffset: 0x459 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
PCIe Remapped CR1 | VarStore: Setup | VarOffset: 0x45B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
PCIe Remapped CR2 | VarStore: Setup | VarOffset: 0x45C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
PCIe Remapped CR3 | VarStore: Setup | VarOffset: 0x45D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
TBT RTD3 Enable | VarStore: Setup | VarOffset: 0x53D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
TBT Power-off delay in ms | VarStore: Setup | VarOffset: 0x53B | Size: 0x2
Min: 0x0 | Max: 0x3A98 | Step: 0x1
ACPI D3Cold settings
TBT RTD3 CLKREQ Enable | VarStore: Setup | VarOffset: 0x53E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI D3Cold settings
TBT RTD3 CLKREQ Delay value | VarStore: Setup | VarOffset: 0x53F | Size: 0x2
Min: 0x0 | Max: 0x7D0 | Step: 0x1
VTIO
Enable VTIO Support | VarStore: Setup | VarOffset: 0x508 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
VTIO
Expose CIO2 SDEV Entry | VarStore: Setup | VarOffset: 0x509 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
VTIO
Expose ISP SDEV Entry | VarStore: Setup | VarOffset: 0x50A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
VTIO
Expose ISP SDEV Entry | VarStore: Setup | VarOffset: 0x50A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
VTIO
Number of Sensor Entries | VarStore: Setup | VarOffset: 0x51A | Size: 0x2
Min: 0x0 | Max: 0x2 | Step: 0x0
VTIO
Flags | VarStore: Setup | VarOffset: 0x68D | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x0
VTIO
Sensor Entry 1 | VarStore: Setup | VarOffset: 0x524 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
VTIO
Sensor Entry 2 | VarStore: Setup | VarOffset: 0x52E | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
VTIO
Expose HECI SDEV Entry | VarStore: Setup | VarOffset: 0x50C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
VTIO
Number of Sensor Entries | VarStore: Setup | VarOffset: 0x51C | Size: 0x2
Min: 0x0 | Max: 0x2 | Step: 0x0
VTIO
Flags | VarStore: Setup | VarOffset: 0x68E | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x0
VTIO
Sensor Entry 1 | VarStore: Setup | VarOffset: 0x526 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
VTIO
Sensor Entry 2 | VarStore: Setup | VarOffset: 0x530 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
VTIO
Expose SPI1 Dev 1E Fun 2 SDEV Entry | VarStore: Setup | VarOffset: 0x50D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
VTIO
Number of Sensor Entries | VarStore: Setup | VarOffset: 0x51E | Size: 0x2
Min: 0x0 | Max: 0x2 | Step: 0x0
VTIO
Flags | VarStore: Setup | VarOffset: 0x68F | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x0
VTIO
Sensor Entry 1 | VarStore: Setup | VarOffset: 0x528 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
VTIO
Sensor Entry 2 | VarStore: Setup | VarOffset: 0x532 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
VTIO
Expose SPI2 Dev 1E Fun 3 SDEV Entry | VarStore: Setup | VarOffset: 0x50E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
VTIO
Number of Sensor Entries | VarStore: Setup | VarOffset: 0x520 | Size: 0x2
Min: 0x0 | Max: 0x2 | Step: 0x0
VTIO
Flags | VarStore: Setup | VarOffset: 0x690 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x0
VTIO
Sensor Entry 1 | VarStore: Setup | VarOffset: 0x52A | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
VTIO
Sensor Entry 2 | VarStore: Setup | VarOffset: 0x534 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
VTIO
Expose XHCI SDEV Entry | VarStore: Setup | VarOffset: 0x50B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
VTIO
Number of USB Devices | VarStore: Setup | VarOffset: 0x554 | Size: 0x1
Min: 0x1 | Max: 0x2 | Step: 0x0
VTIO
Flags | VarStore: Setup | VarOffset: 0x691 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x0
VTIO
Attributes | VarStore: Setup | VarOffset: 0x555 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
VTIO
Root Port Number | VarStore: Setup | VarOffset: 0x557 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
VTIO
VID | VarStore: Setup | VarOffset: 0x559 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
VTIO
PID | VarStore: Setup | VarOffset: 0x55D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
VTIO
Revision | VarStore: Setup | VarOffset: 0x561 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
VTIO
Interface Number | VarStore: Setup | VarOffset: 0x565 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
VTIO
Class | VarStore: Setup | VarOffset: 0x567 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
VTIO
Subclass | VarStore: Setup | VarOffset: 0x569 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
VTIO
Protocol | VarStore: Setup | VarOffset: 0x56B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
VTIO
ACPI Path String Offset | VarStore: Setup | VarOffset: 0x56D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
VTIO
ACPI Path String Length | VarStore: Setup | VarOffset: 0x571 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
VTIO
Firmware Hash [255:192] | VarStore: Setup | VarOffset: 0x58D | Size: 0x8
Min: 0x0 | Max: 0xFFFFFFFFFFFFFFFF | Step: 0x1
VTIO
Firmware Hash [191:128] | VarStore: Setup | VarOffset: 0x585 | Size: 0x8
Min: 0x0 | Max: 0xFFFFFFFFFFFFFFFF | Step: 0x1
VTIO
Firmware Hash [127:64] | VarStore: Setup | VarOffset: 0x57D | Size: 0x8
Min: 0x0 | Max: 0xFFFFFFFFFFFFFFFF | Step: 0x1
VTIO
Firmware Hash [63:0] | VarStore: Setup | VarOffset: 0x575 | Size: 0x8
Min: 0x0 | Max: 0xFFFFFFFFFFFFFFFF | Step: 0x1
VTIO
ACPI Path Name
VTIO
Attributes | VarStore: Setup | VarOffset: 0x556 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
VTIO
Root Port Number | VarStore: Setup | VarOffset: 0x558 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
VTIO
VID | VarStore: Setup | VarOffset: 0x55B | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
VTIO
PID | VarStore: Setup | VarOffset: 0x55F | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
VTIO
Revision | VarStore: Setup | VarOffset: 0x563 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
VTIO
Interface Number | VarStore: Setup | VarOffset: 0x566 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
VTIO
Class | VarStore: Setup | VarOffset: 0x568 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
VTIO
Subclass | VarStore: Setup | VarOffset: 0x56A | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
VTIO
Protocol | VarStore: Setup | VarOffset: 0x56C | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
VTIO
ACPI Path String Offset | VarStore: Setup | VarOffset: 0x56F | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
VTIO
ACPI Path String Length | VarStore: Setup | VarOffset: 0x573 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
VTIO
Firmware Hash [255:192] | VarStore: Setup | VarOffset: 0x5AD | Size: 0x8
Min: 0x0 | Max: 0xFFFFFFFFFFFFFFFF | Step: 0x1
VTIO
Firmware Hash [191:128] | VarStore: Setup | VarOffset: 0x5A5 | Size: 0x8
Min: 0x0 | Max: 0xFFFFFFFFFFFFFFFF | Step: 0x1
VTIO
Firmware Hash [127:64] | VarStore: Setup | VarOffset: 0x59D | Size: 0x8
Min: 0x0 | Max: 0xFFFFFFFFFFFFFFFF | Step: 0x1
VTIO
Firmware Hash [63:0] | VarStore: Setup | VarOffset: 0x595 | Size: 0x8
Min: 0x0 | Max: 0xFFFFFFFFFFFFFFFF | Step: 0x1
VTIO
ACPI Path Name
TCSS Platform Setting
USBC connector manager selection | VarStore: Setup | VarOffset: 0x6B6 | Size: 0x1
Disabled: 0x0
Enable UCSI Device: 0x1
Enable UCMC Device: 0x2
TCSS Platform Setting
PD PS_ON mode selection | VarStore: Setup | VarOffset: 0x6BB | Size: 0x1
Disabled: 0x0
Enable PD PS_ON: 0x1
Enable PD PS_ON Override: 0x2
OverClocking Performance Menu
OverClocking Feature | VarStore: CpuSetup | VarOffset: 0x1B7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
OverClocking Performance Menu
Per-core HT Disable | VarStore: CpuSetup | VarOffset: 0x24B | Size: 0x2
Min: 0x0 | Max: 0x1FF | Step: 0x1
OverClocking Performance Menu
Intel Speed Optimizer | VarStore: CpuSetup | VarOffset: 0x2C9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
OverClocking Performance Menu
WDT Enable | VarStore: PchSetup | VarOffset: 0x20 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
OverClocking Performance Menu
XTU Interface | VarStore: CpuSetup | VarOffset: 0x1B8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
OverClocking Performance Menu
BCLK Aware Adaptive Voltage | VarStore: CpuSetup | VarOffset: 0x207 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
OverClocking Performance Menu
Unlimited ICCMAX | VarStore: CpuSetup | VarOffset: 0x2CA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
OverClocking Performance Menu
PVD Ratio Threshold | VarStore: CpuSetup | VarOffset: 0x2D7 | Size: 0x1
Min: 0x0 | Max: 0x28 | Step: 0x1
Processor
Core Ratio Extension Mode | VarStore: CpuSetup | VarOffset: 0x2CB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Processor
Per Core Ratio Override | VarStore: CpuSetup | VarOffset: 0x2CC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Processor
Core Max OC Ratio | VarStore: CpuSetup | VarOffset: 0x1B9 | Size: 0x1
Min: 0x0 | Max: 0x78 | Step: 0x1
Processor
Core 0 Max Ratio | VarStore: CpuSetup | VarOffset: 0x2CD | Size: 0x1
Min: 0x0 | Max: 0x78 | Step: 0x1
Processor
Core 1 Max Ratio | VarStore: CpuSetup | VarOffset: 0x2CE | Size: 0x1
Min: 0x0 | Max: 0x78 | Step: 0x1
Processor
Core 2 Max Ratio | VarStore: CpuSetup | VarOffset: 0x2CF | Size: 0x1
Min: 0x0 | Max: 0x78 | Step: 0x1
Processor
Core 3 Max Ratio | VarStore: CpuSetup | VarOffset: 0x2D0 | Size: 0x1
Min: 0x0 | Max: 0x78 | Step: 0x1
Processor
Core 4 Max Ratio | VarStore: CpuSetup | VarOffset: 0x2D1 | Size: 0x1
Min: 0x0 | Max: 0x78 | Step: 0x1
Processor
Core 5 Max Ratio | VarStore: CpuSetup | VarOffset: 0x2D2 | Size: 0x1
Min: 0x0 | Max: 0x78 | Step: 0x1
Processor
Core 6 Max Ratio | VarStore: CpuSetup | VarOffset: 0x2D3 | Size: 0x1
Min: 0x0 | Max: 0x78 | Step: 0x1
Processor
Core 7 Max Ratio | VarStore: CpuSetup | VarOffset: 0x2D4 | Size: 0x1
Min: 0x0 | Max: 0x78 | Step: 0x1
Processor
Core 8 Max Ratio | VarStore: CpuSetup | VarOffset: 0x2D5 | Size: 0x1
Min: 0x0 | Max: 0x78 | Step: 0x1
Processor
Core 9 Max Ratio | VarStore: CpuSetup | VarOffset: 0x2D6 | Size: 0x1
Min: 0x0 | Max: 0x78 | Step: 0x1
Processor
Core Voltage Mode | VarStore: CpuSetup | VarOffset: 0x1BA | Size: 0x1
Adaptive: 0x0
Override: 0x1
Processor
Core Voltage Override | VarStore: CpuSetup | VarOffset: 0x1BB | Size: 0x2
Min: 0x0 | Max: 0x7D0 | Step: 0x1
Processor
Core Extra Turbo Voltage | VarStore: CpuSetup | VarOffset: 0x1C0 | Size: 0x2
Min: 0x0 | Max: 0x7D0 | Step: 0x1
Processor
VF Point Offset Mode | VarStore: CpuSetup | VarOffset: 0x26B | Size: 0x1
Legacy: 0x0
Selection: 0x1
Processor
Core Voltage Offset | VarStore: CpuSetup | VarOffset: 0x1BD | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
Offset Prefix | VarStore: CpuSetup | VarOffset: 0x1BF | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 1 Offset | VarStore: CpuSetup | VarOffset: 0x26D | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 1 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x28B | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 2 Offset | VarStore: CpuSetup | VarOffset: 0x26F | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 2 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x28C | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 3 Offset | VarStore: CpuSetup | VarOffset: 0x271 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 3 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x28D | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 4 Offset | VarStore: CpuSetup | VarOffset: 0x273 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 4 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x28E | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 5 Offset | VarStore: CpuSetup | VarOffset: 0x275 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 5 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x28F | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 6 Offset | VarStore: CpuSetup | VarOffset: 0x277 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 6 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x290 | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 7 Offset | VarStore: CpuSetup | VarOffset: 0x279 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 7 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x291 | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 8 Offset | VarStore: CpuSetup | VarOffset: 0x27B | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 8 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x292 | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 9 Offset | VarStore: CpuSetup | VarOffset: 0x27D | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 9 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x293 | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 10 Offset | VarStore: CpuSetup | VarOffset: 0x27F | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 10 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x294 | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 11 Offset | VarStore: CpuSetup | VarOffset: 0x281 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 11 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x295 | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 12 Offset | VarStore: CpuSetup | VarOffset: 0x283 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 12 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x296 | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 13 Offset | VarStore: CpuSetup | VarOffset: 0x285 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 13 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x297 | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 14 Offset | VarStore: CpuSetup | VarOffset: 0x287 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 14 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x298 | Size: 0x1
+: 0x0
-: 0x1
Processor
VF Point 15 Offset | VarStore: CpuSetup | VarOffset: 0x289 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Processor
VF Point 15 Offset Prefix | VarStore: CpuSetup | VarOffset: 0x299 | Size: 0x1
+: 0x0
-: 0x1
Processor
AVX2 Ratio Offset | VarStore: CpuSetup | VarOffset: 0x1C2 | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Processor
AVX2 Voltage Guardband Scale Factor | VarStore: CpuSetup | VarOffset: 0x269 | Size: 0x1
Min: 0x0 | Max: 0xC8 | Step: 0x1
Processor
AVX512 Voltage Guardband Scale Factor | VarStore: CpuSetup | VarOffset: 0x26A | Size: 0x1
Min: 0x0 | Max: 0xC8 | Step: 0x1
Processor
TjMax Offset | VarStore: CpuSetup | VarOffset: 0x1EC | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Processor
TVB Ratio Clipping | VarStore: CpuSetup | VarOffset: 0x231 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Processor
TVB Voltage Optimizations | VarStore: CpuSetup | VarOffset: 0x232 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Ring
Ring Max OC Ratio | VarStore: CpuSetup | VarOffset: 0x1C4 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Ring
Ring Down Bin | VarStore: CpuSetup | VarOffset: 0x1C5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Ring
Min Ring Ratio Limit | VarStore: CpuSetup | VarOffset: 0x20A | Size: 0x1
Min: 0x0 | Max: 0x53 | Step: 0x1
Ring
Max Ring Ratio Limit | VarStore: CpuSetup | VarOffset: 0x20C | Size: 0x1
Min: 0x0 | Max: 0x53 | Step: 0x1
GT
GT OverClocking Frequency | VarStore: SaSetup | VarOffset: 0x248 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
GT
GT Voltage Mode | VarStore: SaSetup | VarOffset: 0x249 | Size: 0x1
Adaptive: 0x0
Override: 0x1
GT
GT Voltage Override | VarStore: SaSetup | VarOffset: 0x24D | Size: 0x2
Min: 0x0 | Max: 0x7D0 | Step: 0x1
GT
GT Extra Turbo Voltage | VarStore: SaSetup | VarOffset: 0x24F | Size: 0x2
Min: 0x0 | Max: 0x7D0 | Step: 0x1
GT
GT Voltage Offset | VarStore: SaSetup | VarOffset: 0x24A | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
GT
Offset Prefix | VarStore: SaSetup | VarOffset: 0x24C | Size: 0x1
+: 0x0
-: 0x1
GT
GT OverClocking Frequency | VarStore: SaSetup | VarOffset: 0x251 | Size: 0x1
Min: 0x0 | Max: 0x3C | Step: 0x1
GT
GT Voltage Mode | VarStore: SaSetup | VarOffset: 0x252 | Size: 0x1
Adaptive: 0x0
Override: 0x1
GT
GT Voltage Override | VarStore: SaSetup | VarOffset: 0x256 | Size: 0x2
Min: 0x0 | Max: 0x7D0 | Step: 0x1
GT
GT Extra Turbo Voltage | VarStore: SaSetup | VarOffset: 0x258 | Size: 0x2
Min: 0x0 | Max: 0x7D0 | Step: 0x1
GT
GTU Voltage Offset | VarStore: SaSetup | VarOffset: 0x253 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
GT
Offset Prefix | VarStore: SaSetup | VarOffset: 0x255 | Size: 0x1
+: 0x0
-: 0x1
Uncore
Uncore Voltage Mode | VarStore: SaSetup | VarOffset: 0x4F5 | Size: 0x1
Adaptive: 0x0
Override: 0x1
Uncore
Uncore Voltage Override | VarStore: SaSetup | VarOffset: 0x4F6 | Size: 0x2
Min: 0x0 | Max: 0x7D0 | Step: 0x1
Uncore
Uncore Extra Turbo Voltage | VarStore: SaSetup | VarOffset: 0x4F8 | Size: 0x2
Min: 0x0 | Max: 0x7D0 | Step: 0x1
Uncore
Uncore Voltage Offset | VarStore: SaSetup | VarOffset: 0x242 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x1
Uncore
Offset Prefix | VarStore: SaSetup | VarOffset: 0x244 | Size: 0x1
+: 0x0
-: 0x1
Platform Voltage Overrides
VccCore Override Enable | VarStore: CpuSetup | VarOffset: 0x218 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Voltage Overrides
VccCore | VarStore: CpuSetup | VarOffset: 0x219 | Size: 0x2
Min: 0x320 | Max: 0x9F6 | Step: 0xA
Platform Voltage Overrides
VccST Override Enable | VarStore: CpuSetup | VarOffset: 0x21B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Voltage Overrides
VccST | VarStore: CpuSetup | VarOffset: 0x21C | Size: 0x2
Min: 0xFA | Max: 0x5DC | Step: 0xA
Platform Voltage Overrides
VccSA Override Enable | VarStore: CpuSetup | VarOffset: 0x21F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Voltage Overrides
VccSA | VarStore: CpuSetup | VarOffset: 0x220 | Size: 0x2
Min: 0xFA | Max: 0x5F0 | Step: 0xA
Platform Voltage Overrides
VccSFR_OC Override Enable | VarStore: CpuSetup | VarOffset: 0x222 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Voltage Overrides
VccSFR_OC | VarStore: CpuSetup | VarOffset: 0x223 | Size: 0x2
Min: 0x3E8 | Max: 0x9D8 | Step: 0xA
Platform Voltage Overrides
VccSFR Override Enable | VarStore: CpuSetup | VarOffset: 0x226 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Voltage Overrides
VccSFR | VarStore: CpuSetup | VarOffset: 0x227 | Size: 0x2
Min: 0x2B2 | Max: 0x802 | Step: 0xA
Platform Voltage Overrides
VccIO Override Enable | VarStore: CpuSetup | VarOffset: 0x22A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Voltage Overrides
VccIO | VarStore: CpuSetup | VarOffset: 0x22B | Size: 0x2
Min: 0x384 | Max: 0x5F0 | Step: 0x5
Platform Voltage Overrides
Core VR Loadline Override | VarStore: CpuSetup | VarOffset: 0x233 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform Voltage Overrides
DC Loadline value | VarStore: CpuSetup | VarOffset: 0x234 | Size: 0x1
-100 uOhm: 0x0
0 uOhm: 0x1
100 uOhm: 0x2
700 uOhm: 0x3
900 uOhm: 0x4
1000 uOhm: 0x5
1200 uOhm: 0x6
1300 uOhm: 0x7
1400 uOhm: 0x8
1500 uOhm: 0x9
1700 uOhm: 0xA
1800 uOhm: 0xB
2100 uOhm: 0xC
Memory Overclocking Menu
Realtime Memory Timing | VarStore: SaSetup | VarOffset: 0x26C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Overclocking Menu
Memory profile | VarStore: SaSetup | VarOffset: 0x18E | Size: 0x1
Default profile: 0x0
Custom profile: 0x1
XMP profile 1: 0x2
XMP profile 2: 0x3
Memory Overclocking Menu
Realtime Memory OverClock | VarStore: SaSetup | VarOffset: 0x4FA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Overclocking Menu
Memory Reference Clock | VarStore: SaSetup | VarOffset: 0xC | Size: 0x1
133: 0x0
100: 0x1
Memory Overclocking Menu
Memory Ratio | VarStore: SaSetup | VarOffset: 0xE | Size: 0x1
Auto: 0x0
3: 0x3
4: 0x4
5: 0x5
6: 0x6
7: 0x7
8: 0x8
9: 0x9
10: 0xA
11: 0xB
12: 0xC
13: 0xD
14: 0xE
15: 0xF
16: 0x10
17: 0x11
18: 0x12
19: 0x13
20: 0x14
21: 0x15
22: 0x16
23: 0x17
24: 0x18
25: 0x19
26: 0x1A
27: 0x1B
28: 0x1C
29: 0x1D
30: 0x1E
31: 0x1F
Memory Overclocking Menu
QCLK Odd Ratio | VarStore: SaSetup | VarOffset: 0xF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Overclocking Menu
tCL | VarStore: SaSetup | VarOffset: 0x10 | Size: 0x1
Min: 0x0 | Max: 0x28 | Step: 0x1
Memory Overclocking Menu
tRCD/tRP | VarStore: SaSetup | VarOffset: 0x16 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Memory Overclocking Menu
tRAS | VarStore: SaSetup | VarOffset: 0x14 | Size: 0x2
Min: 0x0 | Max: 0x5A | Step: 0x1
Memory Overclocking Menu
tCWL | VarStore: SaSetup | VarOffset: 0x11 | Size: 0x1
Min: 0x0 | Max: 0x22 | Step: 0x1
Memory Overclocking Menu
tFAW | VarStore: SaSetup | VarOffset: 0x12 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Memory Overclocking Menu
tREFI | VarStore: SaSetup | VarOffset: 0x17 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Memory Overclocking Menu
tRFC | VarStore: SaSetup | VarOffset: 0x19 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
Memory Overclocking Menu
tRRD | VarStore: SaSetup | VarOffset: 0x1B | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Memory Overclocking Menu
tRRD_L | VarStore: SaSetup | VarOffset: 0x1C | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Memory Overclocking Menu
tRRD_S | VarStore: SaSetup | VarOffset: 0x1D | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Memory Overclocking Menu
tRTP | VarStore: SaSetup | VarOffset: 0x1E | Size: 0x1
Min: 0x0 | Max: 0x10 | Step: 0x1
Memory Overclocking Menu
tWR | VarStore: SaSetup | VarOffset: 0x1F | Size: 0x1
Auto: 0x0
5: 0x5
6: 0x6
7: 0x7
8: 0x8
10: 0xA
12: 0xC
14: 0xE
16: 0x10
18: 0x12
20: 0x14
22: 0x16
24: 0x18
28: 0x1C
30: 0x1E
32: 0x20
34: 0x22
38: 0x26
40: 0x28
44: 0x2C
Memory Overclocking Menu
tWTR | VarStore: SaSetup | VarOffset: 0x20 | Size: 0x1
Min: 0x0 | Max: 0x1C | Step: 0x1
Memory Overclocking Menu
tWTR_L | VarStore: SaSetup | VarOffset: 0x21 | Size: 0x1
Min: 0x0 | Max: 0x3C | Step: 0x1
Memory Overclocking Menu
tWTR_S | VarStore: SaSetup | VarOffset: 0x22 | Size: 0x1
Min: 0x0 | Max: 0x1C | Step: 0x1
Memory Overclocking Menu
Memory Voltage | VarStore: SaSetup | VarOffset: 0x3 | Size: 0x2
Default: 0x0
0.60 Volts: 0x258
1.10 Volts: 0x44C
1.20 Volts: 0x4B0
1.25 Volts: 0x4E2
1.30 Volts: 0x514
1.35 Volts: 0x546
1.40 Volts: 0x578
1.45 Volts: 0x5AA
1.50 Volts: 0x5DC
1.55 Volts: 0x60E
1.60 Volts: 0x640
1.65 Volts: 0x672
Memory Overclocking Menu
NMode | VarStore: SaSetup | VarOffset: 0x23 | Size: 0x1
Min: 0x0 | Max: 0x2 | Step: 0x1
Memory Overclocking Menu
Command Rate Support | VarStore: SaSetup | VarOffset: 0x27A | Size: 0x1
Disabled: 0x0
1 CMD: 0x1
2 CMDs: 0x2
3 CMDs: 0x3
4 CMDs: 0x4
5 CMDs: 0x5
6 CMDs: 0x6
7 CMDs: 0x7
Memory Overclocking Menu
DllBwEn Override | VarStore: SaSetup | VarOffset: 0x501 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Overclocking Menu
DllBwEn[0] | VarStore: SaSetup | VarOffset: 0x7 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Memory Overclocking Menu
DllBwEn[1] | VarStore: SaSetup | VarOffset: 0x8 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Memory Overclocking Menu
DllBwEn[2] | VarStore: SaSetup | VarOffset: 0x9 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Memory Overclocking Menu
DllBwEn[3] | VarStore: SaSetup | VarOffset: 0xA | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Turn Around Timing
tRd2RdSG | VarStore: SaSetup | VarOffset: 0x1D7 | Size: 0x1
Min: 0x0 | Max: 0x36 | Step: 0x1
Turn Around Timing
tRd2RdDG | VarStore: SaSetup | VarOffset: 0x1D8 | Size: 0x1
Min: 0x0 | Max: 0x36 | Step: 0x1
Turn Around Timing
tRd2RdDR | VarStore: SaSetup | VarOffset: 0x1D9 | Size: 0x1
Min: 0x0 | Max: 0x36 | Step: 0x1
Turn Around Timing
tRd2RdDD | VarStore: SaSetup | VarOffset: 0x1DA | Size: 0x1
Min: 0x0 | Max: 0x36 | Step: 0x1
Turn Around Timing
tRd2WrSG | VarStore: SaSetup | VarOffset: 0x1E3 | Size: 0x1
Min: 0x0 | Max: 0x36 | Step: 0x1
Turn Around Timing
tRd2WrDG | VarStore: SaSetup | VarOffset: 0x1E4 | Size: 0x1
Min: 0x0 | Max: 0x36 | Step: 0x1
Turn Around Timing
tRd2WrDR | VarStore: SaSetup | VarOffset: 0x1E5 | Size: 0x1
Min: 0x0 | Max: 0x36 | Step: 0x1
Turn Around Timing
tRd2WrDD | VarStore: SaSetup | VarOffset: 0x1E6 | Size: 0x1
Min: 0x0 | Max: 0x36 | Step: 0x1
Turn Around Timing
tWr2RdSG | VarStore: SaSetup | VarOffset: 0x1DB | Size: 0x1
Min: 0x0 | Max: 0x56 | Step: 0x1
Turn Around Timing
tWr2RdDG | VarStore: SaSetup | VarOffset: 0x1DC | Size: 0x1
Min: 0x0 | Max: 0x36 | Step: 0x1
Turn Around Timing
tWr2RdDR | VarStore: SaSetup | VarOffset: 0x1DD | Size: 0x1
Min: 0x0 | Max: 0x36 | Step: 0x1
Turn Around Timing
tWr2RdDD | VarStore: SaSetup | VarOffset: 0x1DE | Size: 0x1
Min: 0x0 | Max: 0x36 | Step: 0x1
Turn Around Timing
tWr2WrSG | VarStore: SaSetup | VarOffset: 0x1DF | Size: 0x1
Min: 0x0 | Max: 0x36 | Step: 0x1
Turn Around Timing
tWr2WrDG | VarStore: SaSetup | VarOffset: 0x1E0 | Size: 0x1
Min: 0x0 | Max: 0x36 | Step: 0x1
Turn Around Timing
tWr2WrDR | VarStore: SaSetup | VarOffset: 0x1E1 | Size: 0x1
Min: 0x0 | Max: 0x36 | Step: 0x1
Turn Around Timing
tWr2WrDD | VarStore: SaSetup | VarOffset: 0x1E2 | Size: 0x1
Min: 0x0 | Max: 0x36 | Step: 0x1
Voltage PLL Trim Controls
Core PLL Voltage Offset | VarStore: CpuSetup | VarOffset: 0x1E7 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Voltage PLL Trim Controls
GT PLL Voltage Offset | VarStore: CpuSetup | VarOffset: 0x1E8 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Voltage PLL Trim Controls
Ring PLL Voltage Offset | VarStore: CpuSetup | VarOffset: 0x1E9 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Voltage PLL Trim Controls
System Agent PLL Voltage Offset | VarStore: CpuSetup | VarOffset: 0x1EA | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Voltage PLL Trim Controls
Memory Controller PLL Voltage Offset | VarStore: CpuSetup | VarOffset: 0x1EB | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
AMT Configuration
USB Provisioning of AMT | VarStore: MeSetup | VarOffset: 0x1F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CIRA Configuration
Activate Remote Assistance Process | VarStore: MeSetup | VarOffset: 0x1D
CIRA Configuration
CIRA Timeout | VarStore: MeSetup | VarOffset: 0x1E | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
ASF Configuration
PET Progress | VarStore: MeSetup | VarOffset: 0x20 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ASF Configuration
WatchDog | VarStore: MeSetup | VarOffset: 0x23 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ASF Configuration
OS Timer | VarStore: MeSetup | VarOffset: 0x24 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
ASF Configuration
BIOS Timer | VarStore: MeSetup | VarOffset: 0x26 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
ASF Configuration
ASF Sensors Table | VarStore: MeSetup | VarOffset: 0x22 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Secure Erase Configuration
Secure Erase Mode | VarStore: Setup | VarOffset: 0x4FD | Size: 0x1
Simulated: 0x0
Real: 0x1
Secure Erase Configuration
Force Secure Erase | VarStore: Setup | VarOffset: 0x4FE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
OEM Flags Settings
MEBx Hotkey Pressed | VarStore: MeSetup | VarOffset: 0x18
OEM Flags Settings
MEBx Selection Screen | VarStore: MeSetup | VarOffset: 0x19
OEM Flags Settings
Hide Unconfigure ME Confirmation Prompt | VarStore: MeSetup | VarOffset: 0x1A
OEM Flags Settings
MEBx OEM Debug Menu Enable | VarStore: MeSetup | VarOffset: 0x1B
OEM Flags Settings
Unconfigure ME | VarStore: MeSetup | VarOffset: 0x1C
MEBx Resolution Settings
Non-UI Mode Resolution | VarStore: MeSetup | VarOffset: 0x28 | Size: 0x1
Auto: 0x0
80x25: 0x1
100x31: 0x2
MEBx Resolution Settings
UI Mode Resolution | VarStore: MeSetup | VarOffset: 0x29 | Size: 0x1
Auto: 0x0
80x25: 0x1
100x31: 0x2
MEBx Resolution Settings
Graphics Mode Resolution | VarStore: MeSetup | VarOffset: 0x2A | Size: 0x1
Auto: 0x0
640x480: 0x1
800x600: 0x2
1024x768: 0x3
Intel ICC
ICC/OC Watchdog Timer | VarStore: Setup | VarOffset: 0x4F2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel ICC
ICC Profile | VarStore: IccAdvancedSetupDataVar | VarOffset: 0x6 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Intel ICC
ICC PLL Shutdown | VarStore: Setup | VarOffset: 0x4F7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel ICC
Clock Frequency | VarStore: IccAdvancedSetupDataVar | VarOffset: 0x0 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Intel ICC
Bclk Change Permanent | VarStore: SaSetup | VarOffset: 0x26D | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Intel ICC
Bclk Change w/o Reset | VarStore: SaSetup | VarOffset: 0x26E | Size: 0x1
Real Time change: 0x0
Permanent, no warm reset: 0x1
Intel ICC
Spread % | VarStore: IccAdvancedSetupDataVar | VarOffset: 0x2 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Intel ICC
| VarStore: IccAdvancedSetupDataVar | VarOffset: 0x3 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x0
Intel ICC
| VarStore: IccAdvancedSetupDataVar | VarOffset: 0x4 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x0
Intel ICC
| VarStore: IccAdvancedSetupDataVar | VarOffset: 0x5 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x0
Intel ICC
| VarStore: IccAdvancedSetupDataVar | VarOffset: 0x7 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x0
Debug Settings
Kernel Debug Serial Port | VarStore: PchSetup | VarOffset: 0x8 | Size: 0x1
Legacy UART: 0x0
SERIALIO UART2: 0x3
Debug Settings
Platform Debug Consent | VarStore: PchSetup | VarOffset: 0x6E0 | Size: 0x1
Disabled: 0x0
Enabled (DCI OOB+[DbC]): 0x1
Enabled (DCI OOB): 0x2
Enabled (USB2 DbC): 0x5
Enabled (USB3 DbC): 0x3
Enabled (XDP/MIPI60): 0x4
Advanced Debug Settings
USB3 Type-C UFP2DFP Kernel/Platform Debug Support | VarStore: PchSetup | VarOffset: 0xA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
No Change: 0x2
Advanced Debug Settings
SLP_S0# Override | VarStore: PchSetup | VarOffset: 0x12 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Auto: 0x2
Advanced Debug Settings
S0ix Override Settings | VarStore: PchSetup | VarOffset: 0x13 | Size: 0x1
No Change: 0x0
DCI OOB: 0x1
USB2 DbC: 0x2
Auto: 0x3
Advanced Debug Settings
USB Overcurrent Override for DbC | VarStore: PchSetup | VarOffset: 0xB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Advanced Debug Settings
PCH Trace Hub Enable Mode | VarStore: PchSetup | VarOffset: 0x6B7 | Size: 0x1
Disabled: 0x0
Target Debugger: 0x1
Host Debugger: 0x2
Advanced Debug Settings
PCH TH Mem Buffer Size 0 | VarStore: PchSetup | VarOffset: 0x6B8 | Size: 0x1
None/OS: 0x0
1MB: 0x1
8MB: 0x2
64MB: 0x3
128MB: 0x4
256MB: 0x5
512MB: 0x6
Advanced Debug Settings
PCH TH Mem Buffer Size 1 | VarStore: PchSetup | VarOffset: 0x6B9 | Size: 0x1
None/OS: 0x0
1MB: 0x1
8MB: 0x2
64MB: 0x3
128MB: 0x4
256MB: 0x5
512MB: 0x6
Advanced Debug Settings
CPU Trace Hub Enable Mode | VarStore: SaSetup | VarOffset: 0x102 | Size: 0x1
Disabled: 0x0
Target Debugger: 0x1
Host Debugger: 0x2
Advanced Debug Settings
CPU TH Mem Buffer Size 0 | VarStore: SaSetup | VarOffset: 0x103 | Size: 0x1
None/OS: 0x0
1MB: 0x1
8MB: 0x2
64MB: 0x3
128MB: 0x4
256MB: 0x5
512MB: 0x6
Advanced Debug Settings
CPU TH Mem Buffer Size 1 | VarStore: SaSetup | VarOffset: 0x104 | Size: 0x1
None/OS: 0x0
1MB: 0x1
8MB: 0x2
64MB: 0x3
128MB: 0x4
256MB: 0x5
512MB: 0x6
Advanced Debug Settings
CPU Run Control | VarStore: CpuSetup | VarOffset: 0xDD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
No Change: 0x2
Advanced Debug Settings
CPU Run Control Lock | VarStore: CpuSetup | VarOffset: 0xDE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Advanced Debug Settings
Processor trace memory allocation | VarStore: CpuSetup | VarOffset: 0xFD | Size: 0x1
Disabled: 0xFF
4KB: 0x0
8KB: 0x1
16KB: 0x2
32KB: 0x3
64KB: 0x4
128KB: 0x5
256KB: 0x6
512KB: 0x7
1MB: 0x8
2MB: 0x9
4MB: 0xA
8MB: 0xB
16MB: 0xC
32MB: 0xD
64MB: 0xE
128MB: 0xF
Advanced Debug Settings
Processor trace | VarStore: CpuSetup | VarOffset: 0xFE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Advanced Debug Settings
Processor Trace OutPut Scheme | VarStore: CpuSetup | VarOffset: 0xFC | Size: 0x1
Single Range Output: 0x0
ToPA Output: 0x1
Advanced Debug Settings
SMM Processor Trace | VarStore: CpuSmm | VarOffset: 0x5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Advanced Debug Settings
JTAG C10 Power Gate | VarStore: CpuSetup | VarOffset: 0x8 | Size: 0x1
Disabled: 0x1
Enabled: 0x0
Advanced Debug Settings
Three Strike Counter | VarStore: CpuSetup | VarOffset: 0x100 | Size: 0x1
Disabled: 0x1
Enabled: 0x0
Advanced Debug Settings
CrashLog Feature | VarStore: Setup | VarOffset: 0x512 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Advanced Debug Settings
CrashLog On All Reset | VarStore: Setup | VarOffset: 0x513 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Advanced Debug Settings
PMC Debug Message Enable | VarStore: PchSetup | VarOffset: 0x6E1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Advanced Debug Settings
CPU Wakeup Timer | VarStore: CpuSetup | VarOffset: 0x208 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Advanced Debug Settings
Delayed Authentication Mode | VarStore: MeSetupStorage | VarOffset: 0xA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Boot Feature
Fast Boot | VarStore: Setup | VarOffset: 0x10 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Boot Feature
Quiet Boot | VarStore: AMITSESetup | VarOffset: 0x51
Boot Feature
Option ROM Messages | VarStore: Setup | VarOffset: 0x7E8 | Size: 0x1
Force BIOS: 0x1
Keep Current: 0x0
Boot Feature
Bootup NumLock State | VarStore: Setup | VarOffset: 0x0 | Size: 0x1
On: 0x1
Off: 0x0
Boot Feature
Wait For "F1" If Error | VarStore: Setup | VarOffset: 0x2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Boot Feature
INT19 Trap Response | VarStore: Setup | VarOffset: 0x7E9 | Size: 0x1
Immediate: 0x1
Postponed: 0x0
Boot Feature
Re-try Boot | VarStore: Setup | VarOffset: 0x4 | Size: 0x1
Disabled: 0x0
Legacy Boot: 0x1
EFI Boot: 0x2
Boot Feature
Quickly Boot Menu by F11 Support | VarStore: Setup | VarOffset: 0xD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Boot Feature
Watch Dog Function | VarStore: Setup | VarOffset: 0x5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Boot Feature
Front USB Port(s) | VarStore: Setup | VarOffset: 0x12 | Size: 0x1
Enabled: 0x0
Disabled: 0x1
Enabled (Dynamic): 0x2
Boot Feature
Rear USB Port(s) | VarStore: Setup | VarOffset: 0x13 | Size: 0x1
Enabled: 0x0
Disabled: 0x1
Enabled (Dynamic): 0x2
Boot Feature
Watch Dog Function Count Down Time | VarStore: Setup | VarOffset: 0x6 | Size: 0x1
5 Minutes: 0x5
10 Minutes: 0xA
15 Minutes: 0xF
Boot Feature
Restore on AC Power Loss | VarStore: Setup | VarOffset: 0x875 | Size: 0x1
BIOS: 0x0
IPMI: 0x1
Boot Feature
Restore on AC Power Loss | VarStore: Setup | VarOffset: 0x876 | Size: 0x1
Stay Off: 0x0
Power On: 0x1
Last State: 0x2
Boot Feature
Power Button Function | VarStore: Setup | VarOffset: 0x877 | Size: 0x1
Instant Off: 0x1
4 Seconds Override: 0x0
Boot Feature
DeepSx Power Policies | VarStore: PchSetup | VarOffset: 0x4 | Size: 0x1
Disabled: 0x0
Enabled in S4-S5/Battery: 0x3
Enabled In S4-S5: 0x4
Boot Feature
The Foreground Color of Hotkey Message | VarStore: Setup | VarOffset: 0x7 | Size: 0x1
Black: 0x0
Blue: 0x1
Green: 0x2
Cyan: 0x3
Red: 0x4
Magenta: 0x5
Brown: 0x6
Light Gray: 0x7
Dark Gray: 0x8
Light Blue: 0x9
Light Green: 0xA
Light Cyan: 0xB
Light Red: 0xC
Light Magenta: 0xD
Yellow: 0xE
White: 0xF
Boot Feature
The Background Color of Hotkey Message | VarStore: Setup | VarOffset: 0x8 | Size: 0x1
Black: 0x0
Blue: 0x1
Green: 0x2
Cyan: 0x3
Red: 0x4
Magenta: 0x5
Brown: 0x6
Light Gray: 0x7
Dark Gray: 0x8
Light Blue: 0x9
Light Green: 0xA
Light Cyan: 0xB
Light Red: 0xC
Light Magenta: 0xD
Yellow: 0xE
White: 0xF
Boot Feature
Hotkey Message in Logo | VarStore: Setup | VarOffset: 0x9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Boot Feature
Boot Procedure Message in | VarStore: Setup | VarOffset: 0xA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Boot Feature
Disaply HotkeyHint/StatusCode/BmcIp Message | VarStore: Setup | VarOffset: 0xB | Size: 0x1
Hide All: 0x0
Hide HotkeyHint/StatusCode: 0x1
Hide HotkeyHint/BmcIp: 0x2
Hide HotkeyHint: 0x3
Hide StatusCode/BmcIp: 0x4
Hide StatusCode: 0x5
Hide BmcIp: 0x6
Display All: 0x7
Trusted Computing
Security Device Support | VarStore: Setup | VarOffset: 0x6CE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Trusted Computing
Disable Block Sid | VarStore: Setup | VarOffset: 0x6E9 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Trusted Computing
Security Device Support | VarStore: Setup | VarOffset: 0x6CE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Trusted Computing
TPM State | VarStore: Setup | VarOffset: 0x6C9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Trusted Computing
Pending Operation | VarStore: Setup | VarOffset: 0x6CA | Size: 0x1
None: 0x0
TPM Clear: 0x5
Trusted Computing
Security Device Support | VarStore: Setup | VarOffset: 0x6CE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Trusted Computing
TCM State | VarStore: Setup | VarOffset: 0x6C9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Trusted Computing
Pending Operation | VarStore: Setup | VarOffset: 0x6CA | Size: 0x1
None: 0x0
TPM Clear: 0x5
Trusted Computing
Intel Trusted Execution Technology | VarStore: CpuSetup | VarOffset: 0xBC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Trusted Computing
Security Device Support | VarStore: Setup | VarOffset: 0x6CE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Trusted Computing
SHA-1 PCR Bank | VarStore: Setup | VarOffset: 0x6E2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Trusted Computing
SHA256 PCR Bank | VarStore: Setup | VarOffset: 0x6E3 | Size: 0x1
Disabled: 0x0
Enabled: 0x2
Trusted Computing
SHA384 PCR Bank | VarStore: Setup | VarOffset: 0x6E4 | Size: 0x1
Disabled: 0x0
Enabled: 0x4
Trusted Computing
SHA512 PCR Bank | VarStore: Setup | VarOffset: 0x6E5 | Size: 0x1
Disabled: 0x0
Enabled: 0x8
Trusted Computing
SM3_256 PCR Bank | VarStore: Setup | VarOffset: 0x6E6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Trusted Computing
Pending Operation | VarStore: Setup | VarOffset: 0x6CA | Size: 0x1
None: 0x0
TPM Clear: 0x1
Trusted Computing
Platform Hierarchy | VarStore: Setup | VarOffset: 0x6D7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Trusted Computing
Storage Hierarchy | VarStore: Setup | VarOffset: 0x6D8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Trusted Computing
Endorsement Hierarchy | VarStore: Setup | VarOffset: 0x6D9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Trusted Computing
TPM 2.0 InterfaceType | VarStore: Setup | VarOffset: 0x6DA | Size: 0x1
CRB: 0x0
TIS: 0x1
Trusted Computing
PH Randomization | VarStore: Setup | VarOffset: 0x6DC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Trusted Computing
Disable Block Sid | VarStore: Setup | VarOffset: 0x6E9 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Trusted Computing
Intel Trusted Execution Technology | VarStore: CpuSetup | VarOffset: 0xBC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI Settings
Enable ACPI Auto Configuration | VarStore: Setup | VarOffset: 0x6EB
ACPI Settings
Enable Hibernation | VarStore: Setup | VarOffset: 0x6EE
ACPI Settings
ACPI Sleep State | VarStore: Setup | VarOffset: 0x6EC | Size: 0x2
Suspend Disabled: 0x0
S3 (Suspend to RAM): 0x2
ACPI Settings
S3 Video Repost | VarStore: Setup | VarOffset: 0x6EF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Demo Board
CRB Test | VarStore: Setup | VarOffset: 0x769
SMART Settings
SMART Self Test | VarStore: Setup | VarOffset: 0x76A
Runtime Error Logging Settings
Runtime Error Logging System Enabling | VarStore: Setup | VarOffset: 0x76B | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Runtime Error Logging Settings
Memory Error Enabling | VarStore: Setup | VarOffset: 0x76C | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Runtime Error Logging Settings
PCI/PCI Error Enabling | VarStore: Setup | VarOffset: 0x76D | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Runtime Error Logging Settings
Corrected Error Enable | VarStore: Setup | VarOffset: 0x76E | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Runtime Error Logging Settings
Uncorrected Error Enable | VarStore: Setup | VarOffset: 0x76F | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Runtime Error Logging Settings
Fatal Error Enable | VarStore: Setup | VarOffset: 0x770 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Runtime Error Logging Settings
Enable PERR propagation | VarStore: Setup | VarOffset: 0x771 | Size: 0x1
Yes: 0x1
No: 0x0
Runtime Error Logging Settings
Enable SERR propagation | VarStore: Setup | VarOffset: 0x772 | Size: 0x1
Yes: 0x1
No: 0x0
Serial Port 1 Configuration
Serial Port 1 | VarStore: PNP0501_0_NV | VarOffset: 0x0
Serial Port 1 Configuration
Change Settings | VarStore: PNP0501_0_NV | VarOffset: 0x1 | Size: 0x1
Auto: 0x0
IO=3F8h; IRQ=4;: 0x1
IO=2F8h; IRQ=4;: 0x2
IO=3E8h; IRQ=4;: 0x3
IO=2E8h; IRQ=4;: 0x4
Serial Port 2 Configuration
Serial Port 2 | VarStore: PNP0501_1_NV | VarOffset: 0x0
Serial Port 2 Configuration
Change Settings | VarStore: PNP0501_0_NV | VarOffset: 0x1 | Size: 0x1
Auto: 0x0
IO=3F8h; IRQ=3;: 0x1
IO=2F8h; IRQ=3;: 0x2
IO=3E8h; IRQ=3;: 0x3
IO=2E8h; IRQ=3;: 0x4
Serial Port 2 Configuration
Serial Port 2 Attribute | VarStore: Setup | VarOffset: 0x774 | Size: 0x1
SOL: 0x3
COM: 0x1
Serial Port Console Redirection
COM1 Console Redirection | VarStore: Setup | VarOffset: 0x78F
Serial Port Console Redirection
SOL/COM2 Console Redirection | VarStore: Setup | VarOffset: 0x790
Serial Port Console Redirection
AMT SOL Console Redirection | VarStore: Setup | VarOffset: 0x791
Serial Port Console Redirection
Console Redirection | VarStore: Setup | VarOffset: 0x7A7
Console Redirection Settings
Out-Of-Band Mgmt Port | VarStore: Setup | VarOffset: 0x7A8 | Size: 0x1
COM1: 0x0
SOL/COM2: 0x1
AMT SOL: 0x2
Console Redirection Settings
Terminal Type | VarStore: Setup | VarOffset: 0x7A9 | Size: 0x1
VT100: 0x0
VT100+: 0x1
VT-UTF8: 0x2
ANSI: 0x3
Console Redirection Settings
Bits Per Second | VarStore: Setup | VarOffset: 0x7AA | Size: 0x1
9600: 0x3
19200: 0x4
57600: 0x6
115200: 0x7
Console Redirection Settings
Flow Control | VarStore: Setup | VarOffset: 0x7AB | Size: 0x1
None: 0x0
Hardware RTS/CTS: 0x1
Software Xon/Xoff: 0x2
Legacy Console Redirection Settings
Redirection COM Port | VarStore: Setup | VarOffset: 0x7AF | Size: 0x1
COM1: 0x0
SOL/COM2: 0x1
AMT SOL: 0x2
COM1
COM1 Terminal Type | VarStore: Setup | VarOffset: 0x792 | Size: 0x1
VT100: 0x0
VT100+: 0x1
VT-UTF8: 0x2
ANSI: 0x3
COM1
COM1 Bits Per Second | VarStore: Setup | VarOffset: 0x780 | Size: 0x1
9600: 0x3
19200: 0x4
38400: 0x5
57600: 0x6
115200: 0x7
COM1
COM1 Data Bits | VarStore: Setup | VarOffset: 0x783 | Size: 0x1
7: 0x7
8: 0x8
COM1
COM1 Parity | VarStore: Setup | VarOffset: 0x786 | Size: 0x1
None: 0x1
Even: 0x2
Odd: 0x3
Mark: 0x4
Space: 0x5
COM1
COM1 Stop Bits | VarStore: Setup | VarOffset: 0x789 | Size: 0x1
1: 0x1
2: 0x3
COM1
COM1 Flow Control | VarStore: Setup | VarOffset: 0x78C | Size: 0x1
None: 0x0
Hardware RTS/CTS: 0x1
COM1
COM1 VT-UTF8 Combo Key Support | VarStore: Setup | VarOffset: 0x795
COM1
COM1 Recorder Mode | VarStore: Setup | VarOffset: 0x798
COM1
COM1 Resolution 100x31 | VarStore: Setup | VarOffset: 0x79B
COM1
COM1 Putty KeyPad | VarStore: Setup | VarOffset: 0x7A1 | Size: 0x1
VT100: 0x1
LINUX: 0x2
XTERMR6: 0x4
SCO: 0x8
ESCN: 0x10
VT400: 0x20
COM1
COM1 Legacy OS Redirection Resolution | VarStore: Setup | VarOffset: 0x79E | Size: 0x1
80x24: 0x0
80x25: 0x1
COM1
COM1 Redirection After BIOS POST | VarStore: Setup | VarOffset: 0x7A4 | Size: 0x1
Always Enable: 0x0
BootLoader: 0x1
SOL/COM2
SOL/COM2 Terminal Type | VarStore: Setup | VarOffset: 0x793 | Size: 0x1
VT100: 0x0
VT100+: 0x1
VT-UTF8: 0x2
ANSI: 0x3
SOL/COM2
SOL/COM2 Bits per second | VarStore: Setup | VarOffset: 0x781 | Size: 0x1
9600: 0x3
19200: 0x4
38400: 0x5
57600: 0x6
115200: 0x7
SOL/COM2
SOL/COM2 Data Bits | VarStore: Setup | VarOffset: 0x784 | Size: 0x1
7: 0x7
8: 0x8
SOL/COM2
SOL/COM2 Parity | VarStore: Setup | VarOffset: 0x787 | Size: 0x1
None: 0x1
Even: 0x2
Odd: 0x3
Mark: 0x4
Space: 0x5
SOL/COM2
SOL/COM2 Stop Bits | VarStore: Setup | VarOffset: 0x78A | Size: 0x1
1: 0x1
2: 0x3
SOL/COM2
SOL/COM2 Flow Control | VarStore: Setup | VarOffset: 0x78D | Size: 0x1
None: 0x0
Hardware RTS/CTS: 0x1
SOL/COM2
SOL/COM2 VT-UTF8 Combo Key Support | VarStore: Setup | VarOffset: 0x796
SOL/COM2
SOL/COM2 Recorder Mode | VarStore: Setup | VarOffset: 0x799
SOL/COM2
SOL/COM2 Resolution 100x31 | VarStore: Setup | VarOffset: 0x79C
SOL/COM2
SOL/COM2 Putty KeyPad | VarStore: Setup | VarOffset: 0x7A2 | Size: 0x1
VT100: 0x1
LINUX: 0x2
XTERMR6: 0x4
SCO: 0x8
ESCN: 0x10
VT400: 0x20
SOL/COM2
SOL/COM2 Legacy OS Redirection Resolution | VarStore: Setup | VarOffset: 0x79F | Size: 0x1
80x24: 0x0
80x25: 0x1
SOL/COM2
SOL/COM2 Redirection After BIOS POST | VarStore: Setup | VarOffset: 0x7A5 | Size: 0x1
Always Enable: 0x0
BootLoader: 0x1
AMT SOL
AMT SOL Terminal Type | VarStore: Setup | VarOffset: 0x794 | Size: 0x1
VT100: 0x0
VT100+: 0x1
VT-UTF8: 0x2
ANSI: 0x3
AMT SOL
AMT SOL Bits per second | VarStore: Setup | VarOffset: 0x782 | Size: 0x1
9600: 0x3
19200: 0x4
38400: 0x5
57600: 0x6
115200: 0x7
AMT SOL
AMT SOL Data Bits | VarStore: Setup | VarOffset: 0x785 | Size: 0x1
7: 0x7
8: 0x8
AMT SOL
AMT SOL Parity | VarStore: Setup | VarOffset: 0x788 | Size: 0x1
None: 0x1
Even: 0x2
Odd: 0x3
Mark: 0x4
Space: 0x5
AMT SOL
AMT SOL Stop Bits | VarStore: Setup | VarOffset: 0x78B | Size: 0x1
1: 0x1
2: 0x3
AMT SOL
AMT SOL Flow Control | VarStore: Setup | VarOffset: 0x78E | Size: 0x1
None: 0x0
Hardware RTS/CTS: 0x1
AMT SOL
AMT SOL VT-UTF8 Combo Key Support | VarStore: Setup | VarOffset: 0x797
AMT SOL
AMT SOL Recorder Mode | VarStore: Setup | VarOffset: 0x79A
AMT SOL
AMT SOL Resolution 100x31 | VarStore: Setup | VarOffset: 0x79D
AMT SOL
AMT SOL Putty KeyPad | VarStore: Setup | VarOffset: 0x7A3 | Size: 0x1
VT100: 0x1
LINUX: 0x2
XTERMR6: 0x4
SCO: 0x8
ESCN: 0x10
VT400: 0x20
AMT SOL
AMT SOL Legacy OS Redirection Resolution | VarStore: Setup | VarOffset: 0x7A0 | Size: 0x1
80x24: 0x0
80x25: 0x1
AMT SOL
AMT SOL Redirection After BIOS POST | VarStore: Setup | VarOffset: 0x7A6 | Size: 0x1
Always Enable: 0x0
BootLoader: 0x1
AMI Graphic Output Protocol Policy
Output Select | VarStore: Setup | VarOffset: 0x7B4 | Size: 0x1
Unknown Device: 0x0
AMI Graphic Output Protocol Policy
Output Select | VarStore: Setup | VarOffset: 0x7B4 | Size: 0x1
Unknown Device: 0x0
Unknown Device: 0x1
AMI Graphic Output Protocol Policy
Output Select | VarStore: Setup | VarOffset: 0x7B4 | Size: 0x1
Unknown Device: 0x0
Unknown Device: 0x1
Unknown Device: 0x2
AMI Graphic Output Protocol Policy
Output Select | VarStore: Setup | VarOffset: 0x7B4 | Size: 0x1
Unknown Device: 0x0
Unknown Device: 0x1
Unknown Device: 0x2
Unknown Device: 0x3
AMI Graphic Output Protocol Policy
Output Select | VarStore: Setup | VarOffset: 0x7B4 | Size: 0x1
Unknown Device: 0x0
Unknown Device: 0x1
Unknown Device: 0x2
Unknown Device: 0x3
Unknown Device: 0x4
AMI Graphic Output Protocol Policy
Output Select | VarStore: Setup | VarOffset: 0x7B4 | Size: 0x1
Unknown Device: 0x0
Unknown Device: 0x1
Unknown Device: 0x2
Unknown Device: 0x3
Unknown Device: 0x4
Unknown Device: 0x5
AMI Graphic Output Protocol Policy
Output Select | VarStore: Setup | VarOffset: 0x7B4 | Size: 0x1
Unknown Device: 0x0
Unknown Device: 0x1
Unknown Device: 0x2
Unknown Device: 0x3
Unknown Device: 0x4
Unknown Device: 0x5
Unknown Device: 0x6
AMI Graphic Output Protocol Policy
Output Select | VarStore: Setup | VarOffset: 0x7B4 | Size: 0x1
Unknown Device: 0x0
Unknown Device: 0x1
Unknown Device: 0x2
Unknown Device: 0x3
Unknown Device: 0x4
Unknown Device: 0x5
Unknown Device: 0x6
Unknown Device: 0x7
AMI Graphic Output Protocol Policy
Brightness Setting | VarStore: Setup | VarOffset: 0x7B5 | Size: 0x4
Min: 0x0 | Max: 0xFFFFFFFF | Step: 0x1
Brightness Setting: 0x0
AMI Graphic Output Protocol Policy
BIST Enable | VarStore: Setup | VarOffset: 0x7B9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SIO Common Setting
Lock Legacy Resources | VarStore: SioSetupData | VarOffset: 0x0
PCI Subsystem Settings
PCI Latency Timer | VarStore: Setup | VarOffset: 0x7BE | Size: 0x1
32 PCI Bus Clocks: 0x20
64 PCI Bus Clocks: 0x40
96 PCI Bus Clocks: 0x60
128 PCI Bus Clocks: 0x80
160 PCI Bus Clocks: 0xA0
192 PCI Bus Clocks: 0xC0
224 PCI Bus Clocks: 0xE0
248 PCI Bus Clocks: 0xF8
PCI Subsystem Settings
PCI-X Latency Timer | VarStore: Setup | VarOffset: 0x7C2 | Size: 0x1
32 PCI Bus Clocks: 0x20
64 PCI Bus Clocks: 0x40
96 PCI Bus Clocks: 0x60
128 PCI Bus Clocks: 0x80
160 PCI Bus Clocks: 0xA0
192 PCI Bus Clocks: 0xC0
224 PCI Bus Clocks: 0xE0
248 PCI Bus Clocks: 0xF8
PCI Subsystem Settings
VGA Palette Snoop | VarStore: Setup | VarOffset: 0x7BF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Subsystem Settings
PERR# Generation | VarStore: Setup | VarOffset: 0x7C0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Subsystem Settings
SERR# Generation | VarStore: Setup | VarOffset: 0x7C1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Subsystem Settings
Above 4G Decoding | VarStore: Setup | VarOffset: 0x7BA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Subsystem Settings
Re-Size BAR Support | VarStore: Setup | VarOffset: 0x7BB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Subsystem Settings
SR-IOV Support | VarStore: Setup | VarOffset: 0x7BC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Subsystem Settings
BME DMA Mitigation | VarStore: Setup | VarOffset: 0x7BD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Subsystem Settings
Don't Reset VC-TC Mapping | VarStore: Setup | VarOffset: 0x7CF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Settings
Relaxed Ordering | VarStore: Setup | VarOffset: 0x7C3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Settings
Extended Tag | VarStore: Setup | VarOffset: 0x7C4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Settings
No Snoop | VarStore: Setup | VarOffset: 0x7C5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Settings
Maximum Payload | VarStore: Setup | VarOffset: 0x7C6 | Size: 0x1
Auto: 0x37
128 Bytes: 0x0
256 Bytes: 0x1
512 Bytes: 0x2
1024 Bytes: 0x3
2048 Bytes: 0x4
4096 Bytes: 0x5
PCI Express Settings
Maximum Read Request | VarStore: Setup | VarOffset: 0x7C7 | Size: 0x1
Auto: 0x37
128 Bytes: 0x0
256 Bytes: 0x1
512 Bytes: 0x2
1024 Bytes: 0x3
2048 Bytes: 0x4
4096 Bytes: 0x5
PCI Express Settings
ASPM Support | VarStore: Setup | VarOffset: 0x7C8 | Size: 0x1
Disabled: 0x0
Auto: 0x37
Force L0s: 0x1
PCI Express Settings
Extended Synch | VarStore: Setup | VarOffset: 0x7C9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Settings
Link Training Retry | VarStore: Setup | VarOffset: 0x7CA | Size: 0x1
Disabled: 0x0
2: 0x2
3: 0x3
5: 0x5
PCI Express Settings
Link Training Timeout (uS) | VarStore: Setup | VarOffset: 0x7CB | Size: 0x2
Min: 0xA | Max: 0x2710 | Step: 0xA
PCI Express Settings
Unpopulated Links | VarStore: Setup | VarOffset: 0x7CD | Size: 0x1
Keep Link ON: 0x0
Disabled: 0x1
PCI Express Settings
Restore PCIE Registers | VarStore: Setup | VarOffset: 0x7CE | Size: 0x1
Enabled: 0xFF
Disabled: 0x0
PCI Express GEN 2 Settings
Completion Timeout | VarStore: Setup | VarOffset: 0x7D0 | Size: 0x1
Default: 0xFF
Shorter: 0x55
Longer: 0xAA
Disabled: 0x0
PCI Express GEN 2 Settings
ARI Forwarding | VarStore: Setup | VarOffset: 0x7D1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express GEN 2 Settings
AtomicOp Requester Enable | VarStore: Setup | VarOffset: 0x7D2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express GEN 2 Settings
AtomicOp Egress Blocking | VarStore: Setup | VarOffset: 0x7D3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express GEN 2 Settings
IDO Request Enable | VarStore: Setup | VarOffset: 0x7D4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express GEN 2 Settings
IDO Completion Enable | VarStore: Setup | VarOffset: 0x7D5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express GEN 2 Settings
LTR Mechanism Enable | VarStore: Setup | VarOffset: 0x7D6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express GEN 2 Settings
End-End TLP Prefix Blocking | VarStore: Setup | VarOffset: 0x7D7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express GEN 2 Settings
Target Link Speed | VarStore: Setup | VarOffset: 0x7D8 | Size: 0x1
Auto: 0x37
Force to 2.5 GT/s: 0x1
Force to 5.0 GT/s: 0x2
Force to 8.0 GT/s: 0x3
Force to 16.0 GT/s: 0x4
PCI Express GEN 2 Settings
Clock Power Management | VarStore: Setup | VarOffset: 0x7DA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express GEN 2 Settings
Compliance SOS | VarStore: Setup | VarOffset: 0x7DB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express GEN 2 Settings
Hardware Autonomous Width | VarStore: Setup | VarOffset: 0x7DC | Size: 0x1
Enabled: 0x0
Disabled: 0x1
PCI Express GEN 2 Settings
Hardware Autonomous Speed | VarStore: Setup | VarOffset: 0x7DD | Size: 0x1
Enabled: 0x0
Disabled: 0x1
USB Configuration
USB Support | VarStore: UsbSupport | VarOffset: 0x0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
Legacy USB Support | VarStore: UsbSupport | VarOffset: 0x1 | Size: 0x1
Enabled: 0x0
Disabled: 0x1
Auto: 0x2
USB Configuration
USB 2.0 Controller Mode | VarStore: UsbSupport | VarOffset: 0x2E | Size: 0x1
HiSpeed: 0x1
FullSpeed: 0x0
USB Configuration
XHCI Legacy Support | VarStore: UsbSupport | VarOffset: 0x2A | Size: 0x1
Enabled: 0x1
Disabled: 0x0
USB Configuration
XHCI Hand-off | VarStore: UsbSupport | VarOffset: 0x2B | Size: 0x1
Enabled: 0x1
Disabled: 0x0
USB Configuration
EHCI Hand-off | VarStore: UsbSupport | VarOffset: 0x2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB Mass Storage Driver Support | VarStore: UsbSupport | VarOffset: 0x2F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB S5 Wakeup Support | VarStore: UsbSupport | VarOffset: 0x30 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB transfer time-out | VarStore: UsbSupport | VarOffset: 0x9 | Size: 0x1
1 sec: 0x1
5 sec: 0x5
10 sec: 0xA
20 sec: 0x14
USB Configuration
Device reset time-out | VarStore: UsbSupport | VarOffset: 0x8 | Size: 0x1
10 sec: 0x0
20 sec: 0x1
30 sec: 0x2
40 sec: 0x3
USB Configuration
Device power-up delay | VarStore: UsbSupport | VarOffset: 0x2C | Size: 0x1
Auto: 0x0
Manual: 0x1
USB Configuration
Device power-up delay in seconds | VarStore: UsbSupport | VarOffset: 0x2D | Size: 0x1
Min: 0x1 | Max: 0x28 | Step: 0x1
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0xA | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0xB | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0xC | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0xD | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0xE | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0xF | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x10 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x11 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x12 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x13 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x14 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x15 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x16 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x17 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x18 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x19 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x1A | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x1B | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x1C | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x1D | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x1E | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x1F | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x20 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x21 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x22 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x23 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x24 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x25 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x26 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x27 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x28 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
USB Configuration
N/A | VarStore: UsbSupport | VarOffset: 0x29 | Size: 0x1
Auto: 0x0
Floppy: 0x1
Forced FDD: 0x2
Hard Disk: 0x3
CD-ROM: 0x4
Network Stack Configuration
Network Stack | VarStore: NetworkStackVar | VarOffset: 0x0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Network Stack Configuration
IPv4 PXE Support | VarStore: NetworkStackVar | VarOffset: 0x1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Network Stack Configuration
IPv4 HTTP Support | VarStore: NetworkStackVar | VarOffset: 0x6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Network Stack Configuration
IPv6 PXE Support | VarStore: NetworkStackVar | VarOffset: 0x2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Network Stack Configuration
IPv6 HTTP Support | VarStore: NetworkStackVar | VarOffset: 0x7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Network Stack Configuration
PXE Boot Wait Time | VarStore: NetworkStackVar | VarOffset: 0x4 | Size: 0x1
Min: 0x0 | Max: 0x5 | Step: 0x1
Network Stack Configuration
Media Detect Count | VarStore: NetworkStackVar | VarOffset: 0x5 | Size: 0x1
Min: 0x1 | Max: 0x32 | Step: 0x1
CSM Configuration
CSM Support | VarStore: Setup | VarOffset: 0x7E7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CSM Configuration
GateA20 Active | VarStore: Setup | VarOffset: 0x7EC | Size: 0x1
Upon Request: 0x0
Always: 0x1
CSM Configuration
Option ROM Messages | VarStore: Setup | VarOffset: 0x7E8 | Size: 0x1
Force BIOS: 0x1
Keep Current: 0x0
CSM Configuration
INT19 Trap Response | VarStore: Setup | VarOffset: 0x7E9 | Size: 0x1
Immediate: 0x1
Postponed: 0x0
CSM Configuration
HDD Connection Order | VarStore: Setup | VarOffset: 0x7EB | Size: 0x1
Adjust: 0x0
Keep: 0x1
CSM Configuration
Boot option filter | VarStore: Setup | VarOffset: 0x7ED | Size: 0x1
UEFI and Legacy: 0x0
Legacy only: 0x1
UEFI only: 0x2
CSM Configuration
Network | VarStore: Setup | VarOffset: 0x7EE | Size: 0x1
Do Not Launch: 0x0
EFI: 0x1
Legacy: 0x2
CSM Configuration
Storage Option ROM/UEFI Driver | VarStore: Setup | VarOffset: 0x7EF | Size: 0x1
Do Not Launch: 0x0
EFI: 0x1
Legacy: 0x2
CSM Configuration
Video | VarStore: Setup | VarOffset: 0x7F0 | Size: 0x1
Do Not Launch: 0x0
EFI: 0x1
Legacy: 0x2
CSM Configuration
Other PCI devices | VarStore: Setup | VarOffset: 0x7F1 | Size: 0x1
Do Not Launch: 0x0
EFI: 0x1
Legacy: 0x2
WHEA Configuration
WHEA Support | VarStore: Setup | VarOffset: 0x7F2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCIe/PCI/PnP Configuration
Video | VarStore: Setup | VarOffset: 0x7F0 | Size: 0x1
Do Not Launch: 0x0
EFI: 0x1
Legacy: 0x2
PCIe/PCI/PnP Configuration
PCI PERR/SERR Support | VarStore: Setup | VarOffset: 0x773 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCIe/PCI/PnP Configuration
Above 4GB MMIO BIOS Assignment | VarStore: SaSetup | VarOffset: 0xFC | Size: 0x1
Enabled: 0x1
Disabled: 0x0
PCIe/PCI/PnP Configuration
SR-IOV Support | VarStore: Setup | VarOffset: 0x7BC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCIe/PCI/PnP Configuration
BME DMA Mitigation | VarStore: Setup | VarOffset: 0x7BD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCIe/PCI/PnP Configuration
Onboard Video Option ROM | VarStore: Setup | VarOffset: 0x89B | Size: 0x1
Disabled: 0x0
Legacy: 0x1
EFI: 0x2
PCIe/PCI/PnP Configuration
NVMe Firmware Source | VarStore: Setup | VarOffset: 0x89C | Size: 0x1
Vendor Defined Firmware: 0x0
AMI Native Support: 0x1
PCIe/PCI/PnP Configuration
Consistent Device Name Support | VarStore: Setup | VarOffset: 0x1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCIe/PCI/PnP Configuration
PCH SLOT4 PCI-E 3.0 X4 (IN X8) OPROM | VarStore: Setup | VarOffset: 0x878 | Size: 0x1
Disabled: 0x0
Legacy: 0x1
EFI: 0x2
PCIe/PCI/PnP Configuration
CPU SLOT6 PCI-E 3.0 X16 OPROM | VarStore: Setup | VarOffset: 0x879 | Size: 0x1
Disabled: 0x0
Legacy: 0x1
EFI: 0x2
PCIe/PCI/PnP Configuration
SLOT2 PCI-E 3.0 X8 OPROM | VarStore: Setup | VarOffset: 0x87A | Size: 0x1
Disabled: 0x0
Legacy: 0x1
EFI: 0x2
PCIe/PCI/PnP Configuration
PCH SLOT7 PCI-E 3.0 X4 OPROM | VarStore: Setup | VarOffset: 0x87B | Size: 0x1
Disabled: 0x0
Legacy: 0x1
EFI: 0x2
PCIe/PCI/PnP Configuration
PCI-E M.2-M1 OPROM | VarStore: Setup | VarOffset: 0x87C | Size: 0x1
Disabled: 0x0
Legacy: 0x1
EFI: 0x2
PCIe/PCI/PnP Configuration
PCI-E M.2-E1 OPROM | VarStore: Setup | VarOffset: 0x87D | Size: 0x1
Disabled: 0x0
Legacy: 0x1
EFI: 0x2
PCIe/PCI/PnP Configuration
PCI / PCIX / PCIe Slot 7 OPROM | VarStore: Setup | VarOffset: 0x87E | Size: 0x1
Disabled: 0x0
Legacy: 0x1
EFI: 0x2
PCIe/PCI/PnP Configuration
PCI / PCIX / PCIe Slot 8 OPROM | VarStore: Setup | VarOffset: 0x87F | Size: 0x1
Disabled: 0x0
Legacy: 0x1
EFI: 0x2
PCIe/PCI/PnP Configuration
PCI / PCIX / PCIe Slot 9 OPROM | VarStore: Setup | VarOffset: 0x880 | Size: 0x1
Disabled: 0x0
Legacy: 0x1
EFI: 0x2
PCIe/PCI/PnP Configuration
PCI / PCIX / PCIe Slot 10 OPROM | VarStore: Setup | VarOffset: 0x881 | Size: 0x1
Disabled: 0x0
Legacy: 0x1
EFI: 0x2
PCIe/PCI/PnP Configuration
PCI / PCIX / PCIe Slot 11 OPROM | VarStore: Setup | VarOffset: 0x882 | Size: 0x1
Disabled: 0x0
Legacy: 0x1
EFI: 0x2
PCIe/PCI/PnP Configuration
Onboard LAN1 Option ROM | VarStore: Setup | VarOffset: 0x886 | Size: 0x1
Disabled: 0x0
PXE: 0x1
EFI: 0x4
PCIe/PCI/PnP Configuration
Onboard LAN1 Option ROM | VarStore: Setup | VarOffset: 0x886 | Size: 0x1
Disabled: 0x0
PXE: 0x1
FCoE: 0x3
EFI: 0x4
PCIe/PCI/PnP Configuration
Onboard LAN2 Option ROM | VarStore: Setup | VarOffset: 0x887 | Size: 0x1
Disabled: 0x0
PXE: 0x1
iSCSI: 0x2
PCIe/PCI/PnP Configuration
Onboard LAN3 Option ROM | VarStore: Setup | VarOffset: 0x888 | Size: 0x1
Disabled: 0x0
PXE: 0x1
PCIe/PCI/PnP Configuration
Onboard LAN4 Option ROM | VarStore: Setup | VarOffset: 0x889 | Size: 0x1
Disabled: 0x0
PXE: 0x1
PCIe/PCI/PnP Configuration
Network Stack | VarStore: NetworkStackVar | VarOffset: 0x0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCIe/PCI/PnP Configuration
IPv4 PXE Support | VarStore: NetworkStackVar | VarOffset: 0x1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCIe/PCI/PnP Configuration
IPv4 HTTP Support | VarStore: NetworkStackVar | VarOffset: 0x6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCIe/PCI/PnP Configuration
IPv6 PXE Support | VarStore: NetworkStackVar | VarOffset: 0x2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCIe/PCI/PnP Configuration
IPv6 HTTP Support | VarStore: NetworkStackVar | VarOffset: 0x7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCIe/PCI/PnP Configuration
PXE Boot Wait Time | VarStore: NetworkStackVar | VarOffset: 0x4 | Size: 0x1
Min: 0x0 | Max: 0x5 | Step: 0x1
PCIe/PCI/PnP Configuration
Media Detect Count | VarStore: NetworkStackVar | VarOffset: 0x5 | Size: 0x1
Min: 0x1 | Max: 0x32 | Step: 0x1
HTTP Boot Configuration
Supermicro HTTP Boot Exist Flag | VarStore: Setup | VarOffset: 0x8D2 | Size: 0x1
NON-EXIST: 0x0
EXIST: 0x1
HTTP Boot Configuration
HTTP Boot Policy | VarStore: Setup | VarOffset: 0x8A7 | Size: 0x1
Apply to all LANs: 0x0
Apply to each LAN: 0x1
Boot Priority #1 instantly: 0x2
HTTP Boot Configuration
HTTPS Boot Checks Hostname | VarStore: Setup | VarOffset: 0x8A8 | Size: 0x1
Enabled: 0x0
Disabled (WARNING: Security Risk!!): 0x1
HTTP Boot Configuration
Instance of Priority 1: | VarStore: Setup | VarOffset: 0x8D3 | Size: 0x1
Min: 0x1 | Max: 0xFF | Step: 0x1
HTTP Boot Configuration
Select IPv4 or IPv6 | VarStore: Setup | VarOffset: 0x8D4 | Size: 0x1
IPv4: 0x0
IPv6: 0x1
HTTP Boot Configuration
Boot Description
HTTP Boot Configuration
Boot URI
HTTP Boot Configuration
Instance of Priority 2: | VarStore: Setup | VarOffset: 0xA6B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
HTTP Boot Configuration
Select IPv4 or IPv6 | VarStore: Setup | VarOffset: 0xA6C | Size: 0x1
IPv4: 0x0
IPv6: 0x1
HTTP Boot Configuration
Boot Description
HTTP Boot Configuration
Boot URI
HTTP Boot Configuration
Instance of Priority 3: | VarStore: Setup | VarOffset: 0xC03 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
HTTP Boot Configuration
Select IPv4 or IPv6 | VarStore: Setup | VarOffset: 0xC04 | Size: 0x1
IPv4: 0x0
IPv6: 0x1
HTTP Boot Configuration
Boot Description
HTTP Boot Configuration
Boot URI
HTTP Boot Configuration
Instance of Priority 4: | VarStore: Setup | VarOffset: 0xD9B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
HTTP Boot Configuration
Select IPv4 or IPv6 | VarStore: Setup | VarOffset: 0xD9C | Size: 0x1
IPv4: 0x0
IPv6: 0x1
HTTP Boot Configuration
Boot Description
HTTP Boot Configuration
Boot URI
Advanced
Hide CSM Support item | VarStore: Setup | VarOffset: 0xFCA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Advanced
Hide SGX items | VarStore: Setup | VarOffset: 0xFC9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-FW Configuration
ME FW Image Re-Flash | VarStore: MeSetup | VarOffset: 0x5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-FW Configuration
TPM Device Selection | VarStore: MeSetup | VarOffset: 0x37 | Size: 0x1
dTPM: 0x0
PTT: 0x1
Security
Hard Drive Security Frozen | VarStore: Setup | VarOffset: 0x19 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Security
Password Check | VarStore: AMITSESetup | VarOffset: 0x50 | Size: 0x1
Setup: 0x0
Always: 0x1
CPU Configuration
CPU Max Performance | VarStore: Setup | VarOffset: 0x1B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
C6DRAM | VarStore: CpuSetup | VarOffset: 0xDF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
Hardware Prefetcher | VarStore: CpuSetup | VarOffset: 0xBA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
Adjacent Cache Line Prefetch | VarStore: CpuSetup | VarOffset: 0xBB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
Intel (VMX) Virtualization Technology | VarStore: CpuSetup | VarOffset: 0xB4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
Active Processor Cores | VarStore: CpuSetup | VarOffset: 0x6 | Size: 0x1
All: 0x0
1: 0x1
2: 0x2
3: 0x3
4: 0x4
5: 0x5
6: 0x6
7: 0x7
8: 0x8
9: 0x9
CPU Configuration
Hyper-Threading | VarStore: CpuSetup | VarOffset: 0x5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
AES | VarStore: CpuSetup | VarOffset: 0xB5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
Boot Performance Mode | VarStore: CpuSetup | VarOffset: 0xE | Size: 0x1
Max Battery: 0x0
Max Non-Turbo Performance: 0x1
Turbo Performance: 0x2
CPU Configuration
Intel(R) SpeedStep(tm) | VarStore: CpuSetup | VarOffset: 0x9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
Intel(R) Speed Shift Technology | VarStore: CpuSetup | VarOffset: 0xB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
Turbo Mode | VarStore: CpuSetup | VarOffset: 0x11 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
Package Power Limit MSR Lock | VarStore: CpuSetup | VarOffset: 0x2B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
Power Limit 1 Override | VarStore: CpuSetup | VarOffset: 0x16 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
Power Limit 1 | VarStore: CpuSetup | VarOffset: 0x12 | Size: 0x4
Min: 0x0 | Max: 0x3E7F83 | Step: 0x7D
CPU Configuration
Power Limit 1 Time Window | VarStore: CpuSetup | VarOffset: 0x17 | Size: 0x1
0: 0x0
1: 0x1
2: 0x2
3: 0x3
4: 0x4
5: 0x5
6: 0x6
7: 0x7
8: 0x8
10: 0xA
12: 0xC
14: 0xE
16: 0x10
20: 0x14
24: 0x18
28: 0x1C
32: 0x20
40: 0x28
48: 0x30
56: 0x38
64: 0x40
80: 0x50
96: 0x60
112: 0x70
128: 0x80
CPU Configuration
Power Limit 2 Override | VarStore: CpuSetup | VarOffset: 0x18 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
Power Limit 2 | VarStore: CpuSetup | VarOffset: 0x19 | Size: 0x4
Min: 0x0 | Max: 0x3E7F83 | Step: 0x7D
CPU Configuration
C-States | VarStore: CpuSetup | VarOffset: 0xF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
Enhanced C-States | VarStore: CpuSetup | VarOffset: 0x10 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
C-State Auto Demotion | VarStore: CpuSetup | VarOffset: 0x39 | Size: 0x1
Disabled: 0x0
C1: 0x1
C3: 0x2
C1 and C3: 0x3
CPU Configuration
C-State Un-Demotion | VarStore: CpuSetup | VarOffset: 0x3A | Size: 0x1
Disabled: 0x0
C1: 0x1
C3: 0x2
C1 and C3: 0x3
CPU Configuration
Package C-State Demotion | VarStore: CpuSetup | VarOffset: 0x3B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
Package C-State Un-Demotion | VarStore: CpuSetup | VarOffset: 0x3C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
C-State Pre-Wake | VarStore: CpuSetup | VarOffset: 0x38 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU Configuration
Package C-State Limit | VarStore: CpuSetup | VarOffset: 0x46 | Size: 0x1
C0/C1: 0x0
C2: 0x1
C3: 0x2
C6: 0x3
C7: 0x4
C7S: 0x5
C8: 0x6
C9: 0x7
C10: 0x8
Cpu Default: 0xFE
Auto: 0xFF
CPU Configuration
MonitorMWait | VarStore: CpuSetup | VarOffset: 0xB7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Connectivity Configuration
CNVi WiFi&BT | VarStore: PchSetup | VarOffset: 0x6D7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Graphics Configuration
Graphics Turbo IMON Current | VarStore: SaSetup | VarOffset: 0x188 | Size: 0x1
Min: 0xE | Max: 0x1F | Step: 0x1
Graphics Configuration
Skip Scanning Of External Gfx Card | VarStore: SaSetup | VarOffset: 0x239 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Graphics Configuration
Primary Display | VarStore: SaSetup | VarOffset: 0x182 | Size: 0x1
Auto: 0x3
IGFX: 0x0
PEG: 0x1
PCI: 0x2
Graphics Configuration
Internal Graphics | VarStore: SaSetup | VarOffset: 0x187 | Size: 0x1
Auto: 0x2
Disabled: 0x0
Enabled: 0x1
Graphics Configuration
GTT Size | VarStore: SaSetup | VarOffset: 0x43 | Size: 0x1
2MB: 0x1
4MB: 0x2
8MB: 0x3
Graphics Configuration
Aperture Size | VarStore: SaSetup | VarOffset: 0x44 | Size: 0x1
128MB: 0x0
256MB: 0x1
512MB: 0x3
1024MB: 0x7
2048MB: 0xF
Graphics Configuration
DVMT Pre-Allocated | VarStore: SaSetup | VarOffset: 0xF7 | Size: 0x1
0M: 0x0
32M: 0x1
64M: 0x2
4M: 0xF0
8M: 0xF1
12M: 0xF2
16M: 0xF3
20M: 0xF4
24M: 0xF5
28M: 0xF6
32M/F7: 0xF7
36M: 0xF8
40M: 0xF9
44M: 0xFA
48M: 0xFB
52M: 0xFC
56M: 0xFD
60M: 0xFE
Graphics Configuration
DVMT Total Gfx Mem | VarStore: SaSetup | VarOffset: 0xF8 | Size: 0x1
128M: 0x1
256M: 0x2
Max: 0x3
Graphics Configuration
PM Support | VarStore: SaSetup | VarOffset: 0x48 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Graphics Configuration
PAVP Enable | VarStore: SaSetup | VarOffset: 0x4A | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Graphics Configuration
Cdynmax Clamping Enable | VarStore: SaSetup | VarOffset: 0x4E | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Graphics Configuration
Graphics Clock Frequency | VarStore: SaSetup | VarOffset: 0x4F | Size: 0x1
337.5 Mhz: 0x0
450 Mhz: 0x1
540 Mhz: 0x2
675 Mhz: 0x3
192 Mhz: 0x0
312 Mhz: 0x2
324 Mhz: 0x3
552 Mhz: 0x5
648 Mhz: 0x7
192 Mhz: 0x0
307.2 Mhz: 0x1
326.4 Mhz: 0x4
556.8 Mhz: 0x6
652.8 Mhz: 0x8
Max CdClock freq based on Reference Clk: 0xFF
Graphics Configuration
Skip CD Clock Init In S3 Resume | VarStore: SaSetup | VarOffset: 0x274 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
External Gfx Card Primary Display Configuration
Primary PCIE | VarStore: Setup | VarOffset: 0x7B1 | Size: 0x1
Auto: 0x0
PCH SLOT4 PCI-E 3.0 X4 (IN X8): 0x1
Memory Configuration
Maximum Memory Frequency | VarStore: SaSetup | VarOffset: 0x18C | Size: 0x2
Auto: 0x0
1067: 0x42B
1200: 0x4B0
1333: 0x535
1400: 0x578
1600: 0x640
1800: 0x708
1867: 0x74B
2000: 0x7D0
2133: 0x855
2200: 0x898
2400: 0x960
2600: 0xA28
2667: 0xA6B
2800: 0xAF0
2933: 0xB75
3000: 0xBB8
3200: 0xC80
3400: 0xD48
3467: 0xD8B
3600: 0xE10
3733: 0xE95
3800: 0xED8
4000: 0xFA0
4200: 0x1068
4267: 0x10AB
4400: 0x1130
4533: 0x11B5
4600: 0x11F8
4800: 0x12C0
5000: 0x1388
5067: 0x13CB
5200: 0x1450
5333: 0x14D5
5400: 0x1518
5600: 0x15E0
5800: 0x16A8
5867: 0x16EB
6000: 0x1770
6133: 0x17F5
6200: 0x1838
Memory Configuration
Max TOLUD | VarStore: SaSetup | VarOffset: 0x18B | Size: 0x1
Dynamic: 0x0
1 GB: 0x1
1.25 GB: 0x2
1.5 GB: 0x3
1.75 GB: 0x4
2 GB: 0x5
2.25 GB: 0x6
2.5 GB: 0x7
2.75 GB: 0x8
3 GB: 0x9
3.25 GB: 0xA
3.5 GB: 0xB
Memory Configuration
Memory Scrambler | VarStore: SaSetup | VarOffset: 0x22D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Force ColdReset | VarStore: SaSetup | VarOffset: 0x22E | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Memory Configuration
Force Single Rank | VarStore: SaSetup | VarOffset: 0x199 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Memory Remap | VarStore: SaSetup | VarOffset: 0x231 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Memory Configuration
MRC Fast Boot | VarStore: SaSetup | VarOffset: 0x190 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Enable RH Prevention | VarStore: SaSetup | VarOffset: 0x234 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Row Hammer Solution | VarStore: SaSetup | VarOffset: 0x235 | Size: 0x1
Hardware RHP: 0x0
2x Refresh: 0x1
Memory Configuration
Refresh Watermarks | VarStore: SaSetup | VarOffset: 0x50D | Size: 0x1
High: 0x1
Low: 0x0
PCH-IO Configuration
PCIe PLL SSC | VarStore: PchSetup | VarOffset: 0x1F | Size: 0x1
Enabled: 0xFF
Disabled: 0x0
PCI Express Configuration
DMI Link ASPM Control | VarStore: PchSetup | VarOffset: 0x4F6 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Configuration
Peer Memory Write Enable | VarStore: PchSetup | VarOffset: 0xD3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
SLOT4 ASPM | VarStore: PchSetup | VarOffset: 0x10E | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
SLOT4 L1 Substates | VarStore: PchSetup | VarOffset: 0x276 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
PCIe Speed | VarStore: PchSetup | VarOffset: 0x246 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI-E M.2-E1
M.2-E1 ASPM | VarStore: PchSetup | VarOffset: 0x115 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI-E M.2-E1
M.2-E1 L1 Substates | VarStore: PchSetup | VarOffset: 0x27D | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI-E M.2-E1
PCIe Speed | VarStore: PchSetup | VarOffset: 0x24D | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI-E M.2-M1
M.2-M1 ASPM | VarStore: PchSetup | VarOffset: 0x11E | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI-E M.2-M1
M.2-M1 L1 Substates | VarStore: PchSetup | VarOffset: 0x286 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI-E M.2-M1
PCIe Speed | VarStore: PchSetup | VarOffset: 0x256 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCH SLOT7 PCI-E 3.0 X4
SLOT7 ASPM | VarStore: PchSetup | VarOffset: 0x122 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCH SLOT7 PCI-E 3.0 X4
SLOT7 L1 Substates | VarStore: PchSetup | VarOffset: 0x28A | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCH SLOT7 PCI-E 3.0 X4
PCIe Speed | VarStore: PchSetup | VarOffset: 0x25A | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
CPU - Power Management Control
Boot Performance Mode | VarStore: CpuSetup | VarOffset: 0xE | Size: 0x1
Max Battery: 0x0
Max Non-Turbo Performance: 0x1
Turbo Performance: 0x2
CPU - Power Management Control
Intel(R) SpeedStep(tm) | VarStore: CpuSetup | VarOffset: 0x9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
C-States | VarStore: CpuSetup | VarOffset: 0xF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Enhanced C-States | VarStore: CpuSetup | VarOffset: 0x10 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
C-State Auto Demotion | VarStore: CpuSetup | VarOffset: 0x39 | Size: 0x1
Disabled: 0x0
C1: 0x1
C3: 0x2
C1 and C3: 0x3
CPU - Power Management Control
C-State Un-Demotion | VarStore: CpuSetup | VarOffset: 0x3A | Size: 0x1
Disabled: 0x0
C1: 0x1
C3: 0x2
C1 and C3: 0x3
CPU - Power Management Control
Package C-State Demotion | VarStore: CpuSetup | VarOffset: 0x3B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Package C-State Un-Demotion | VarStore: CpuSetup | VarOffset: 0x3C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
C-State Pre-Wake | VarStore: CpuSetup | VarOffset: 0x38 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
IO MWAIT Redirection | VarStore: CpuSetup | VarOffset: 0x43 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
CPU - Power Management Control
Package C-State Limit | VarStore: CpuSetup | VarOffset: 0x46 | Size: 0x1
C0/C1: 0x0
C2: 0x1
C3: 0x2
C6: 0x3
C7: 0x4
C7S: 0x5
C8: 0x6
C9: 0x7
C10: 0x8
Cpu Default: 0xFE
Auto: 0xFF
CPU - Power Management Control
Package C-State Workaround | VarStore: Setup | VarOffset: 0xF88 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
GT - Power Management Control
RC6(Render Standby) | VarStore: SaSetup | VarOffset: 0x3E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
GT - Power Management Control
Maximum GT Frequency | VarStore: SaSetup | VarOffset: 0x50 | Size: 0x1
Default Max Frequency: 0xFF
100Mhz: 0x2
150Mhz: 0x3
200Mhz: 0x4
250Mhz: 0x5
300Mhz: 0x6
350Mhz: 0x7
400Mhz: 0x8
450Mhz: 0x9
500Mhz: 0xA
550Mhz: 0xB
600Mhz: 0xC
650Mhz: 0xD
700Mhz: 0xE
750Mhz: 0xF
800Mhz: 0x10
850Mhz: 0x11
900Mhz: 0x12
950Mhz: 0x13
1000Mhz: 0x14
1050Mhz: 0x15
1100Mhz: 0x16
1150Mhz: 0x17
1200Mhz: 0x18
GT - Power Management Control
Disable Turbo GT Frequency | VarStore: SaSetup | VarOffset: 0x51 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
SATA And RST Configuration
SATA Controller(s) | VarStore: PchSetup | VarOffset: 0x43 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
SATA And RST Configuration
SATA Mode Selection | VarStore: PchSetup | VarOffset: 0x44 | Size: 0x1
AHCI: 0x0
RAID: 0x1
SATA And RST Configuration
SATA Interrupt Selection | VarStore: PchSetup | VarOffset: 0x45 | Size: 0x1
Msix: 0x0
Msi: 0x1
Legacy: 0x2
SATA And RST Configuration
PCIe Storage Dev On Port 1 | VarStore: PchSetup | VarOffset: 0xB8 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 2 | VarStore: PchSetup | VarOffset: 0xB9 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 3 | VarStore: PchSetup | VarOffset: 0xBA | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 4 | VarStore: PchSetup | VarOffset: 0xBB | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 5 | VarStore: PchSetup | VarOffset: 0xBC | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 6 | VarStore: PchSetup | VarOffset: 0xBD | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 7 | VarStore: PchSetup | VarOffset: 0xBE | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 8 | VarStore: PchSetup | VarOffset: 0xBF | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 9 | VarStore: PchSetup | VarOffset: 0xC0 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 10 | VarStore: PchSetup | VarOffset: 0xC1 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 11 | VarStore: PchSetup | VarOffset: 0xC2 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 12 | VarStore: PchSetup | VarOffset: 0xC3 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 13 | VarStore: PchSetup | VarOffset: 0xC4 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 14 | VarStore: PchSetup | VarOffset: 0xC5 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 15 | VarStore: PchSetup | VarOffset: 0xC6 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 16 | VarStore: PchSetup | VarOffset: 0xC7 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIE M.2-M1 | VarStore: PchSetup | VarOffset: 0xC8 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 18 | VarStore: PchSetup | VarOffset: 0xC9 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 19 | VarStore: PchSetup | VarOffset: 0xCA | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 20 | VarStore: PchSetup | VarOffset: 0xCB | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 21 | VarStore: PchSetup | VarOffset: 0xCC | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 22 | VarStore: PchSetup | VarOffset: 0xCD | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 23 | VarStore: PchSetup | VarOffset: 0xCE | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 24 | VarStore: PchSetup | VarOffset: 0xCF | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
RAID Device ID | VarStore: PchSetup | VarOffset: 0x8D | Size: 0x1
iRST Mode: 0x0
Alternate: 0x1
RSTe Mode: 0x2
SATA And RST Configuration
Storage Option ROM/UEFI Driver | VarStore: Setup | VarOffset: 0x7EF | Size: 0x1
Do Not Launch: 0x0
EFI: 0x1
Legacy: 0x2
SATA And RST Configuration
Teton Glacier Mode | VarStore: PchSetup | VarOffset: 0x6E8 | Size: 0x1
Dynamic Configuration for Hybrid Storage Device Enable: 0x1
Disabled: 0x0
SATA And RST Configuration
Aggressive LPM Support | VarStore: PchSetup | VarOffset: 0x8E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Hot Plug | VarStore: PchSetup | VarOffset: 0x4E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Spin Up Device | VarStore: PchSetup | VarOffset: 0x5E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
SATA Device Type | VarStore: PchSetup | VarOffset: 0x6E | Size: 0x1
Hard Disk Drive: 0x0
Solid State Drive: 0x1
SATA And RST Configuration
Hot Plug | VarStore: PchSetup | VarOffset: 0x4F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Spin Up Device | VarStore: PchSetup | VarOffset: 0x5F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
SATA Device Type | VarStore: PchSetup | VarOffset: 0x6F | Size: 0x1
Hard Disk Drive: 0x0
Solid State Drive: 0x1
SATA And RST Configuration
Hot Plug | VarStore: PchSetup | VarOffset: 0x50 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Spin Up Device | VarStore: PchSetup | VarOffset: 0x60 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
SATA Device Type | VarStore: PchSetup | VarOffset: 0x70 | Size: 0x1
Hard Disk Drive: 0x0
Solid State Drive: 0x1
SATA And RST Configuration
Hot Plug | VarStore: PchSetup | VarOffset: 0x51 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Spin Up Device | VarStore: PchSetup | VarOffset: 0x61 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
SATA Device Type | VarStore: PchSetup | VarOffset: 0x71 | Size: 0x1
Hard Disk Drive: 0x0
Solid State Drive: 0x1
System Agent (SA) Configuration
VT-d | VarStore: SaSetup | VarOffset: 0xFB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
System Agent (SA) Configuration
Software Guard Extensions (SGX) | VarStore: CpuSetup | VarOffset: 0xE0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Software Controlled: 0x2
System Agent (SA) Configuration
Select Owner EPOCH Input Type | VarStore: CpuSetup | VarOffset: 0xE1 | Size: 0x1
No Change In Owner EPOCHs: 0x0
Change To New Random Owner EPOCHs: 0x1
Manual User Defined Owner EPOCHs: 0x2
System Agent (SA) Configuration
Software Guard Extensions Epoch 0 | VarStore: CpuSetupSgxEpochData | VarOffset: 0x0 | Size: 0x8
Min: 0x0 | Max: 0xFFFFFFFFFFFFFFFF | Step: 0x1
System Agent (SA) Configuration
Software Guard Extensions Epoch 1 | VarStore: CpuSetupSgxEpochData | VarOffset: 0x8 | Size: 0x8
Min: 0x0 | Max: 0xFFFFFFFFFFFFFFFF | Step: 0x1
System Agent (SA) Configuration
PRMRR Size | VarStore: CpuSetup | VarOffset: 0xE7 | Size: 0x4
Invalid PRMRR: 0x0
32MB: 0x2000000
64MB: 0x4000000
128MB: 0x8000000
256MB: 0x10000000
System Agent (SA) Configuration
GNA Device (B0:D8:F0) | VarStore: SaSetup | VarOffset: 0xFD | Size: 0x1
Enabled: 0x1
Disabled: 0x0
System Agent (SA) Configuration
X2APIC Opt Out | VarStore: SaSetup | VarOffset: 0x105 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
PEG Port Configuration
Enable Root Port | VarStore: SaSetup | VarOffset: 0x5F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Auto: 0x2
PEG Port Configuration
Max Link Speed | VarStore: SaSetup | VarOffset: 0x63 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PEG Port Configuration
Enable Root Port | VarStore: SaSetup | VarOffset: 0x280 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
Max Link Speed | VarStore: SaSetup | VarOffset: 0x319 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PEG Port Configuration
Max Link Width | VarStore: SaSetup | VarOffset: 0x67 | Size: 0x1
Auto: 0x0
Force X1: 0x1
Force X2: 0x2
Force X4: 0x3
Force X8: 0x4
PEG Port Configuration
ASPM | VarStore: SaSetup | VarOffset: 0x57 | Size: 0x1
Disabled: 0x0
Auto: 0x4
ASPM L0s: 0x1
ASPM L1: 0x2
ASPM L0sL1: 0x3
PEG Port Configuration
ASPM L0s | VarStore: SaSetup | VarOffset: 0x5B | Size: 0x1
Root Port Only: 0x1
Endpoint Port Only: 0x2
Both Root and Endpoint Ports: 0x3
PEG Port Configuration
Power Limit Value | VarStore: SaSetup | VarOffset: 0xDA | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
PEG Port Configuration
Power Limit Scale | VarStore: SaSetup | VarOffset: 0xD6 | Size: 0x1
1.0x: 0x0
0.1x: 0x1
0.01x: 0x2
0.001x: 0x3
PEG Port Configuration
ASPM | VarStore: SaSetup | VarOffset: 0x325 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PEG Port Configuration
Enable Root Port | VarStore: SaSetup | VarOffset: 0x60 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Auto: 0x2
PEG Port Configuration
Max Link Speed | VarStore: SaSetup | VarOffset: 0x64 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PEG Port Configuration
Enable Root Port | VarStore: SaSetup | VarOffset: 0x281 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
Max Link Speed | VarStore: SaSetup | VarOffset: 0x31A | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PEG Port Configuration
Max Link Width | VarStore: SaSetup | VarOffset: 0x68 | Size: 0x1
Auto: 0x0
Force X1: 0x1
Force X2: 0x2
Force X4: 0x3
PEG Port Configuration
ASPM | VarStore: SaSetup | VarOffset: 0x58 | Size: 0x1
Disabled: 0x0
Auto: 0x4
ASPM L0s: 0x1
ASPM L1: 0x2
ASPM L0sL1: 0x3
PEG Port Configuration
ASPM L0s | VarStore: SaSetup | VarOffset: 0x5C | Size: 0x1
Root Port Only: 0x1
Endpoint Port Only: 0x2
Both Root and Endpoint Ports: 0x3
PEG Port Configuration
Power Limit Value | VarStore: SaSetup | VarOffset: 0xDB | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
PEG Port Configuration
Power Limit Scale | VarStore: SaSetup | VarOffset: 0xD7 | Size: 0x1
1.0x: 0x0
0.1x: 0x1
0.01x: 0x2
0.001x: 0x3
PEG Port Configuration
ASPM | VarStore: SaSetup | VarOffset: 0x326 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
ACPI Settings
ACPI Sleep State | VarStore: Setup | VarOffset: 0x6EC | Size: 0x2
Suspend Disabled: 0x0
S3 (Suspend to RAM): 0x2
ACPI Settings
WHEA Support | VarStore: Setup | VarOffset: 0x7F2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI Settings
High Precision Event Timer | VarStore: PchSetup | VarOffset: 0x1A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI Settings
Native PCIE Enable | VarStore: Setup | VarOffset: 0x21 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ACPI Settings
Native ASPM | VarStore: Setup | VarOffset: 0x22 | Size: 0x1
Auto: 0x2
Enabled: 0x1
Disabled: 0x0
ACPI Settings
PCI AER Support | VarStore: Setup | VarOffset: 0xF89 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
DMI/OPI Configuration
DMI Link ASPM Control | VarStore: SaSetup | VarOffset: 0x17E | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
DMI/OPI Configuration
DMI Extended Sync Control | VarStore: SaSetup | VarOffset: 0x17F | Size: 0x1
Enabled: 0x1
Disabled: 0x0
DMI/OPI Configuration
DMI De-emphasis Control | VarStore: SaSetup | VarOffset: 0x109 | Size: 0x1
-6 dB: 0x0
-3.5 dB: 0x1
Chipset
Firmware Configuration | VarStore: Setup | VarOffset: 0x1E | Size: 0x1
Ignore Policy Update: 0x0
Production: 0x1
Test: 0x2
Chipset
Type C Support | VarStore: Setup | VarOffset: 0x548 | Size: 0x1
Platform-POR: 0x0
Enabled: 0x1
Disabled: 0x2
Memory Configuration
MRC ULT Safe Config | VarStore: SaSetup | VarOffset: 0x232 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Safe Mode Support | VarStore: SaSetup | VarOffset: 0x19C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Memory Test on Warm Boot | VarStore: SaSetup | VarOffset: 0x279 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Maximum Memory Frequency | VarStore: SaSetup | VarOffset: 0x18C | Size: 0x2
Auto: 0x0
1067: 0x42B
1200: 0x4B0
1333: 0x535
1400: 0x578
1600: 0x640
1800: 0x708
1867: 0x74B
2000: 0x7D0
2133: 0x855
2200: 0x898
2400: 0x960
2600: 0xA28
2667: 0xA6B
2800: 0xAF0
2933: 0xB75
3000: 0xBB8
3200: 0xC80
3400: 0xD48
3467: 0xD8B
3600: 0xE10
3733: 0xE95
3800: 0xED8
4000: 0xFA0
4200: 0x1068
4267: 0x10AB
4400: 0x1130
4533: 0x11B5
4600: 0x11F8
4800: 0x12C0
5000: 0x1388
5067: 0x13CB
5200: 0x1450
5333: 0x14D5
5400: 0x1518
5600: 0x15E0
5800: 0x16A8
5867: 0x16EB
6000: 0x1770
6133: 0x17F5
6200: 0x1838
Memory Configuration
HOB Buffer Size | VarStore: SaSetup | VarOffset: 0x189 | Size: 0x1
Auto: 0x0
1B: 0x1
1KB: 0x2
Max (assuming 63KB total HOB size): 0x3
Memory Configuration
ECC Support | VarStore: SaSetup | VarOffset: 0x18A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Max TOLUD | VarStore: SaSetup | VarOffset: 0x18B | Size: 0x1
Dynamic: 0x0
1 GB: 0x1
1.25 GB: 0x2
1.5 GB: 0x3
1.75 GB: 0x4
2 GB: 0x5
2.25 GB: 0x6
2.5 GB: 0x7
2.75 GB: 0x8
3 GB: 0x9
3.25 GB: 0xA
3.5 GB: 0xB
Memory Configuration
DDR Speed Control | VarStore: SaSetup | VarOffset: 0x1A9 | Size: 0x1
Auto: 0x0
Manual: 0x1
Memory Configuration
SA GV Low Freq | VarStore: SaSetup | VarOffset: 0x1A5 | Size: 0x2
MRC default: 0x0
1067: 0x42B
1200: 0x4B0
1333: 0x535
1400: 0x578
1600: 0x640
1800: 0x708
1867: 0x74B
2133: 0x855
2400: 0x960
2667: 0xA6B
2933: 0xB75
3200: 0xC80
Memory Configuration
SA GV Mid Freq | VarStore: SaSetup | VarOffset: 0x1A7 | Size: 0x2
MRC default: 0x0
1067: 0x42B
1333: 0x535
1600: 0x640
1800: 0x708
1867: 0x74B
2000: 0x7D0
2133: 0x855
2400: 0x960
2667: 0xA6B
2933: 0xB75
3200: 0xC80
Memory Configuration
SA GV Low Gear | VarStore: SaSetup | VarOffset: 0x1AA | Size: 0x1
Gear1: 0x0
Gear2: 0x1
Memory Configuration
SA GV Mid Gear | VarStore: SaSetup | VarOffset: 0x1AB | Size: 0x1
Gear1: 0x0
Gear2: 0x1
Memory Configuration
SA GV High Gear | VarStore: SaSetup | VarOffset: 0x1AC | Size: 0x1
Gear1: 0x0
Gear2: 0x1
Memory Configuration
Retrain on Fast Fail | VarStore: SaSetup | VarOffset: 0x19B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
RMT on Fast | VarStore: SaSetup | VarOffset: 0x397 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
BER Support | VarStore: SaSetup | VarOffset: 0x19F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Enable RH Prevention | VarStore: SaSetup | VarOffset: 0x234 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Row Hammer Solution | VarStore: SaSetup | VarOffset: 0x235 | Size: 0x1
Hardware RHP: 0x0
2x Refresh: 0x1
Memory Configuration
RH Activation Probability | VarStore: SaSetup | VarOffset: 0x236 | Size: 0x1
1/2^1: 0x1
1/2^2: 0x2
1/2^3: 0x3
1/2^4: 0x4
1/2^5: 0x5
1/2^6: 0x6
1/2^7: 0x7
1/2^8: 0x8
1/2^9: 0x9
1/2^10: 0xA
1/2^11: 0xB
1/2^12: 0xC
1/2^13: 0xD
1/2^14: 0xE
1/2^15: 0xF
Memory Configuration
Refresh Watermarks | VarStore: SaSetup | VarOffset: 0x50D | Size: 0x1
High: 0x1
Low: 0x0
Memory Configuration
Exit On Failure (MRC) | VarStore: SaSetup | VarOffset: 0x237 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Probeless Trace | VarStore: SaSetup | VarOffset: 0x1A0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Memory Trace | VarStore: SaSetup | VarOffset: 0x1A1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
GDXC IOT size | VarStore: SaSetup | VarOffset: 0x1A2 | Size: 0x1
Min: 0x0 | Max: 0x80 | Step: 0x1
Memory Configuration
GDXC MOT size | VarStore: SaSetup | VarOffset: 0x1A3 | Size: 0x1
Min: 0x0 | Max: 0x80 | Step: 0x1
Memory Configuration
Enable/Disable IED (Intel Enhanced Debug) | VarStore: SaSetup | VarOffset: 0x101 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Memory Configuration
Ch Hash Support | VarStore: SaSetup | VarOffset: 0x193 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Ch Hash Mask | VarStore: SaSetup | VarOffset: 0x194 | Size: 0x2
Min: 0x0 | Max: 0x3FFF | Step: 0x1
Memory Configuration
Ch Hash Interleaved Bit | VarStore: SaSetup | VarOffset: 0x196 | Size: 0x1
BIT6: 0x0
BIT7: 0x1
BIT8: 0x2
BIT9: 0x3
BIT10: 0x4
BIT11: 0x5
BIT12: 0x6
BIT13: 0x7
Memory Configuration
Per Bank Refresh | VarStore: SaSetup | VarOffset: 0x197 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Strong Weak Leaker | VarStore: SaSetup | VarOffset: 0x198 | Size: 0x1
Min: 0x1 | Max: 0x7 | Step: 0x1
Memory Configuration
Memory Scrambler | VarStore: SaSetup | VarOffset: 0x22D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Force ColdReset | VarStore: SaSetup | VarOffset: 0x22E | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Memory Configuration
Channel A DIMM Control | VarStore: SaSetup | VarOffset: 0x22F | Size: 0x1
Enable both DIMMs: 0x0
Disable DIMM0: 0x1
Disable DIMM1: 0x2
Disable both DIMMs: 0x3
Memory Configuration
Channel B DIMM Control | VarStore: SaSetup | VarOffset: 0x230 | Size: 0x1
Enable both DIMMs: 0x0
Disable DIMM0: 0x1
Disable DIMM1: 0x2
Disable both DIMMs: 0x3
Memory Configuration
Force Single Rank | VarStore: SaSetup | VarOffset: 0x199 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Memory Remap | VarStore: SaSetup | VarOffset: 0x231 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Memory Configuration
Time Measure | VarStore: SaSetup | VarOffset: 0x18F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
DLL Weak Lock Support | VarStore: SaSetup | VarOffset: 0x512 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Pwr Down Idle Timer | VarStore: SaSetup | VarOffset: 0x511 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Configuration
MRC Fast Boot | VarStore: SaSetup | VarOffset: 0x190 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Train On Warm boot | VarStore: SaSetup | VarOffset: 0x27B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Rank Margin Tool Per Task | VarStore: SaSetup | VarOffset: 0x191 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Training Tracing | VarStore: SaSetup | VarOffset: 0x192 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
Lpddr Mem WL Set | VarStore: SaSetup | VarOffset: 0x19A | Size: 0x1
Set A: 0x0
Set B: 0x1
Memory Configuration
BDAT ACPI Table Support | VarStore: SaSetup | VarOffset: 0x1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Configuration
BDAT Memory Test Type | VarStore: SaSetup | VarOffset: 0x19D | Size: 0x1
Rank Margin Tool Rank: 0x0
Rank Margin Tool Bit: 0x1
Margin 2D: 0x2
Memory Configuration
Rank Margin Tool Loop Count | VarStore: SaSetup | VarOffset: 0x19E | Size: 0x1
Min: 0x0 | Max: 0x20 | Step: 0x1
Memory Configuration
Lpddr Dram Odt | VarStore: SaSetup | VarOffset: 0x27C | Size: 0x1
Auto: 0x2
Enabled: 0x1
Disabled: 0x0
Memory Configuration
DDR4 Skip Refresh Enable | VarStore: SaSetup | VarOffset: 0x27D | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Memory Configuration
Disable Page Close Idle Timeout | VarStore: SaSetup | VarOffset: 0x238 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
System Agent (SA) Configuration
Stop Grant Configuration | VarStore: SaSetup | VarOffset: 0x180 | Size: 0x1
Auto: 0x1
Manual: 0x0
System Agent (SA) Configuration
Number of Stop Grant Cycles | VarStore: SaSetup | VarOffset: 0x181 | Size: 0x1
Min: 0x1 | Max: 0x3F | Step: 0x0
System Agent (SA) Configuration
VT-d | VarStore: SaSetup | VarOffset: 0xFB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
System Agent (SA) Configuration
Control Iommu Pre-boot Behavior | VarStore: Setup | VarOffset: 0x552 | Size: 0x1
Disable IOMMU: 0x0
Enable IOMMU during boot: 0x1
System Agent (SA) Configuration
CHAP Device (B0:D7:F0) | VarStore: SaSetup | VarOffset: 0xF9 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
System Agent (SA) Configuration
Thermal Device (B0:D4:F0) | VarStore: SaSetup | VarOffset: 0xFA | Size: 0x1
Enabled: 0x1
Disabled: 0x0
System Agent (SA) Configuration
GNA Device (B0:D8:F0) | VarStore: SaSetup | VarOffset: 0xFD | Size: 0x1
Enabled: 0x1
Disabled: 0x0
System Agent (SA) Configuration
CRID Support | VarStore: SaSetup | VarOffset: 0x23A | Size: 0x1
Enabled: 0x1
Disabled: 0x0
System Agent (SA) Configuration
Above 4GB MMIO BIOS Assignment | VarStore: SaSetup | VarOffset: 0xFC | Size: 0x1
Enabled: 0x1
Disabled: 0x0
System Agent (SA) Configuration
X2APIC Opt Out | VarStore: SaSetup | VarOffset: 0x105 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
System Agent (SA) Configuration
Dma Control Guarantee | VarStore: SaSetup | VarOffset: 0x106 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
System Agent (SA) Configuration
eDRAM Mode | VarStore: SaSetup | VarOffset: 0x100 | Size: 0x1
SW Mode eDRAM Off: 0x0
SW Mode eDRAM On: 0x1
eDRAM HW Mode: 0x2
System Agent (SA) Configuration
PCIE Resizable BAR Support | VarStore: SaSetup | VarOffset: 0x500 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Graphics Configuration
Graphics Turbo IMON Current | VarStore: SaSetup | VarOffset: 0x188 | Size: 0x1
Min: 0xE | Max: 0x1F | Step: 0x1
Graphics Configuration
Skip Scanning Of External Gfx Card | VarStore: SaSetup | VarOffset: 0x239 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Graphics Configuration
Primary Display | VarStore: SaSetup | VarOffset: 0x182 | Size: 0x1
Auto: 0x3
IGFX: 0x0
PEG: 0x1
PCI: 0x2
SG: 0x4
Graphics Configuration
SG Delay After Hold Reset | VarStore: SaSetup | VarOffset: 0x183 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x0
Graphics Configuration
SG Delay After Hold Reset | VarStore: SaSetup | VarOffset: 0x185 | Size: 0x2
Min: 0x0 | Max: 0x3E8 | Step: 0x0
Graphics Configuration
Internal Graphics | VarStore: SaSetup | VarOffset: 0x187 | Size: 0x1
Auto: 0x2
Disabled: 0x0
Enabled: 0x1
Graphics Configuration
GTT Size | VarStore: SaSetup | VarOffset: 0x43 | Size: 0x1
2MB: 0x1
4MB: 0x2
8MB: 0x3
Graphics Configuration
Aperture Size | VarStore: SaSetup | VarOffset: 0x44 | Size: 0x1
128MB: 0x0
256MB: 0x1
512MB: 0x3
1024MB: 0x7
2048MB: 0xF
Graphics Configuration
PSMI SUPPORT | VarStore: SaSetup | VarOffset: 0x45 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Graphics Configuration
PSMI Region Size | VarStore: SaSetup | VarOffset: 0x46 | Size: 0x1
32MB: 0x0
288MB: 0x1
544MB: 0x2
800MB: 0x3
1024MB: 0x4
Graphics Configuration
DVMT Pre-Allocated | VarStore: SaSetup | VarOffset: 0xF7 | Size: 0x1
0M: 0x0
32M: 0x1
64M: 0x2
4M: 0xF0
8M: 0xF1
12M: 0xF2
16M: 0xF3
20M: 0xF4
24M: 0xF5
28M: 0xF6
32M/F7: 0xF7
36M: 0xF8
40M: 0xF9
44M: 0xFA
48M: 0xFB
52M: 0xFC
56M: 0xFD
60M: 0xFE
Graphics Configuration
DVMT Total Gfx Mem | VarStore: SaSetup | VarOffset: 0xF8 | Size: 0x1
128M: 0x1
256M: 0x2
Max: 0x3
Graphics Configuration
DFD Restore | VarStore: SaSetup | VarOffset: 0x27E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Graphics Configuration
Intel Graphics Pei Display Peim | VarStore: SaSetup | VarOffset: 0x49 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Graphics Configuration
ALS Support | VarStore: SaSetup | VarOffset: 0x40 | Size: 0x1
Enabled: 0x2
Disabled: 0x0
Graphics Configuration
VDD Enable | VarStore: SaSetup | VarOffset: 0x47 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Graphics Configuration
PM Support | VarStore: SaSetup | VarOffset: 0x48 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Graphics Configuration
RC1p Support | VarStore: SaSetup | VarOffset: 0x27F | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Graphics Configuration
PAVP Enable | VarStore: SaSetup | VarOffset: 0x4A | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Graphics Configuration
Cdynmax Clamping Enable | VarStore: SaSetup | VarOffset: 0x4E | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Graphics Configuration
Graphics Clock Frequency | VarStore: SaSetup | VarOffset: 0x4F | Size: 0x1
337.5 Mhz: 0x0
450 Mhz: 0x1
540 Mhz: 0x2
675 Mhz: 0x3
192 Mhz: 0x0
312 Mhz: 0x2
324 Mhz: 0x3
552 Mhz: 0x5
648 Mhz: 0x7
192 Mhz: 0x0
307.2 Mhz: 0x1
326.4 Mhz: 0x4
556.8 Mhz: 0x6
652.8 Mhz: 0x8
Max CdClock freq based on Reference Clk: 0xFF
Graphics Configuration
Skip CD Clock Init In S3 Resume | VarStore: SaSetup | VarOffset: 0x274 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Graphics Configuration
GOP Config Driver Enable | VarStore: SaSetup | VarOffset: 0x4B | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Graphics Configuration
T3 Timing | VarStore: SaSetup | VarOffset: 0x4C | Size: 0x1
Min: 0x0 | Max: 0xFA | Step: 0x1
Graphics Configuration
Enable Display Audio Link in Pre-OS | VarStore: SaSetup | VarOffset: 0x507 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Graphics Configuration
IUER Button Enable | VarStore: SaSetup | VarOffset: 0x23F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
DMI/OPI Configuration
DMI Max Link Speed | VarStore: SaSetup | VarOffset: 0x107 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
DMI/OPI Configuration
DMI Gen3 Eq Phase 2 | VarStore: SaSetup | VarOffset: 0x10A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Auto: 0x2
DMI/OPI Configuration
DMI Gen3 Eq Phase 3 Method | VarStore: SaSetup | VarOffset: 0x10B | Size: 0x1
Auto: 0x0
Adaptive Hardware Equalization: 0x1
Adaptive Software Equalization: 0x2
Static Equalization: 0x3
Disabled: 0x4
DMI/OPI Configuration
Program Static Phase1 Eq | VarStore: SaSetup | VarOffset: 0x10C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
DMI/OPI Configuration
DMI Link ASPM Control | VarStore: SaSetup | VarOffset: 0x17E | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
DMI/OPI Configuration
DMI Extended Sync Control | VarStore: SaSetup | VarOffset: 0x17F | Size: 0x1
Enabled: 0x1
Disabled: 0x0
DMI/OPI Configuration
DMI De-emphasis Control | VarStore: SaSetup | VarOffset: 0x109 | Size: 0x1
-6 dB: 0x0
-3.5 dB: 0x1
DMI/OPI Configuration
DMI IOT | VarStore: SaSetup | VarOffset: 0x108 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
DMI/OPI Configuration
CDR Relock for CPU DMI | VarStore: SaSetup | VarOffset: 0x4FF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
DMI/OPI Configuration
New FOM for CPU DMI | VarStore: SaSetup | VarOffset: 0x506 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
DMI/OPI Configuration
Error Flag Reset Assertion for CPU DMI | VarStore: SaSetup | VarOffset: 0x50C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
DMI/OPI Configuration
Manual Ana Save Restore for CPU DMI | VarStore: SaSetup | VarOffset: 0x510 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Gen3 Root Port Preset value for each Lane
Lane 0 | VarStore: SaSetup | VarOffset: 0x10D | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 1 | VarStore: SaSetup | VarOffset: 0x10E | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 2 | VarStore: SaSetup | VarOffset: 0x10F | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 3 | VarStore: SaSetup | VarOffset: 0x110 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 0 | VarStore: SaSetup | VarOffset: 0x115 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 1 | VarStore: SaSetup | VarOffset: 0x116 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 2 | VarStore: SaSetup | VarOffset: 0x117 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 3 | VarStore: SaSetup | VarOffset: 0x118 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 0 | VarStore: SaSetup | VarOffset: 0x11D | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 1 | VarStore: SaSetup | VarOffset: 0x11E | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 2 | VarStore: SaSetup | VarOffset: 0x11F | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 3 | VarStore: SaSetup | VarOffset: 0x120 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 RxCTLE Control
Bundle0 | VarStore: SaSetup | VarOffset: 0x125 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Gen3 RxCTLE Control
Bundle1 | VarStore: SaSetup | VarOffset: 0x126 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
PEG Port Configuration
Enable Root Port | VarStore: SaSetup | VarOffset: 0x5F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Auto: 0x2
PEG Port Configuration
Max Link Speed | VarStore: SaSetup | VarOffset: 0x63 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PEG Port Configuration
Max Link Width | VarStore: SaSetup | VarOffset: 0x67 | Size: 0x1
Auto: 0x0
Force X1: 0x1
Force X2: 0x2
Force X4: 0x3
Force X8: 0x4
PEG Port Configuration
Power Down Unused Lanes | VarStore: SaSetup | VarOffset: 0x6B | Size: 0x1
Disabled: 0x0
Auto: 0x1
PEG Port Configuration
Gen3 Eq Phase 2 | VarStore: SaSetup | VarOffset: 0x77 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Auto: 0x2
PEG Port Configuration
Gen3 Eq Phase 3 Method | VarStore: SaSetup | VarOffset: 0x73 | Size: 0x1
Auto: 0x0
Adaptive Hardware Equalization: 0x1
Adaptive Software Equalization: 0x2
Static Equalization: 0x3
Disabled: 0x4
PEG Port Configuration
ASPM | VarStore: SaSetup | VarOffset: 0x57 | Size: 0x1
Disabled: 0x0
Auto: 0x4
ASPM L0s: 0x1
ASPM L1: 0x2
ASPM L0sL1: 0x3
PEG Port Configuration
ASPM L0s | VarStore: SaSetup | VarOffset: 0x5B | Size: 0x1
Root Port Only: 0x1
Endpoint Port Only: 0x2
Both Root and Endpoint Ports: 0x3
PEG Port Configuration
De-emphasis Control | VarStore: SaSetup | VarOffset: 0x7B | Size: 0x1
-6 dB: 0x0
-3.5 dB: 0x1
PEG Port Configuration
OBFF | VarStore: SaSetup | VarOffset: 0x87 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
LTR | VarStore: SaSetup | VarOffset: 0x83 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
Power Limit Value | VarStore: SaSetup | VarOffset: 0xDA | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
PEG Port Configuration
Power Limit Scale | VarStore: SaSetup | VarOffset: 0xD6 | Size: 0x1
1.0x: 0x0
0.1x: 0x1
0.01x: 0x2
0.001x: 0x3
PEG Port Configuration
PEG0 Physical Slot Number | VarStore: SaSetup | VarOffset: 0xDE | Size: 0x2
Min: 0x0 | Max: 0x1FFF | Step: 0x1
PEG Port Configuration
PEG0 Hotplug | VarStore: SaSetup | VarOffset: 0xD2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
Extra Bus Reserved | VarStore: SaSetup | VarOffset: 0xE6 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PEG Port Configuration
Reseved Memory | VarStore: SaSetup | VarOffset: 0xE9 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PEG Port Configuration
Reserved I/O | VarStore: SaSetup | VarOffset: 0xEF | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PEG Port Configuration
Enable Root Port | VarStore: SaSetup | VarOffset: 0x60 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Auto: 0x2
PEG Port Configuration
Max Link Speed | VarStore: SaSetup | VarOffset: 0x64 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PEG Port Configuration
Max Link Width | VarStore: SaSetup | VarOffset: 0x68 | Size: 0x1
Auto: 0x0
Force X1: 0x1
Force X2: 0x2
Force X4: 0x3
PEG Port Configuration
Power Down Unused Lanes | VarStore: SaSetup | VarOffset: 0x6C | Size: 0x1
Disabled: 0x0
Auto: 0x1
PEG Port Configuration
Gen3 Eq Phase 2 | VarStore: SaSetup | VarOffset: 0x78 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Auto: 0x2
PEG Port Configuration
Gen3 Eq Phase 3 Method | VarStore: SaSetup | VarOffset: 0x74 | Size: 0x1
Auto: 0x0
Adaptive Hardware Equalization: 0x1
Adaptive Software Equalization: 0x2
Static Equalization: 0x3
Disabled: 0x4
PEG Port Configuration
ASPM | VarStore: SaSetup | VarOffset: 0x58 | Size: 0x1
Disabled: 0x0
Auto: 0x4
ASPM L0s: 0x1
ASPM L1: 0x2
ASPM L0sL1: 0x3
PEG Port Configuration
ASPM L0s | VarStore: SaSetup | VarOffset: 0x5C | Size: 0x1
Root Port Only: 0x1
Endpoint Port Only: 0x2
Both Root and Endpoint Ports: 0x3
PEG Port Configuration
De-emphasis Control | VarStore: SaSetup | VarOffset: 0x7C | Size: 0x1
-6 dB: 0x0
-3.5 dB: 0x1
PEG Port Configuration
OBFF | VarStore: SaSetup | VarOffset: 0x88 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
LTR | VarStore: SaSetup | VarOffset: 0x84 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
Power Limit Value | VarStore: SaSetup | VarOffset: 0xDB | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
PEG Port Configuration
Power Limit Scale | VarStore: SaSetup | VarOffset: 0xD7 | Size: 0x1
1.0x: 0x0
0.1x: 0x1
0.01x: 0x2
0.001x: 0x3
PEG Port Configuration
PEG1 Physical Slot Number | VarStore: SaSetup | VarOffset: 0xE0 | Size: 0x2
Min: 0x0 | Max: 0x1FFF | Step: 0x1
PEG Port Configuration
PEG1 Hotplug | VarStore: SaSetup | VarOffset: 0xD3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
Extra Bus Reserved | VarStore: SaSetup | VarOffset: 0xE7 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PEG Port Configuration
Reseved Memory | VarStore: SaSetup | VarOffset: 0xEB | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PEG Port Configuration
Reserved I/O | VarStore: SaSetup | VarOffset: 0xF0 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PEG Port Configuration
Enable Root Port | VarStore: SaSetup | VarOffset: 0x61 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Auto: 0x2
PEG Port Configuration
Max Link Speed | VarStore: SaSetup | VarOffset: 0x65 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PEG Port Configuration
Max Link Width | VarStore: SaSetup | VarOffset: 0x69 | Size: 0x1
Auto: 0x0
Force X1: 0x1
Force X2: 0x2
PEG Port Configuration
Power Down Unused Lanes | VarStore: SaSetup | VarOffset: 0x6D | Size: 0x1
Disabled: 0x0
Auto: 0x1
PEG Port Configuration
Gen3 Eq Phase 2 | VarStore: SaSetup | VarOffset: 0x79 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Auto: 0x2
PEG Port Configuration
Gen3 Eq Phase 3 Method | VarStore: SaSetup | VarOffset: 0x75 | Size: 0x1
Auto: 0x0
Adaptive Hardware Equalization: 0x1
Adaptive Software Equalization: 0x2
Static Equalization: 0x3
Disabled: 0x4
PEG Port Configuration
ASPM | VarStore: SaSetup | VarOffset: 0x59 | Size: 0x1
Disabled: 0x0
Auto: 0x4
ASPM L0s: 0x1
ASPM L1: 0x2
ASPM L0sL1: 0x3
PEG Port Configuration
ASPM L0s | VarStore: SaSetup | VarOffset: 0x5D | Size: 0x1
Root Port Only: 0x1
Endpoint Port Only: 0x2
Both Root and Endpoint Ports: 0x3
PEG Port Configuration
De-emphasis Control | VarStore: SaSetup | VarOffset: 0x7D | Size: 0x1
-6 dB: 0x0
-3.5 dB: 0x1
PEG Port Configuration
OBFF | VarStore: SaSetup | VarOffset: 0x89 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
LTR | VarStore: SaSetup | VarOffset: 0x85 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
Power Limit Value | VarStore: SaSetup | VarOffset: 0xDC | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
PEG Port Configuration
Power Limit Scale | VarStore: SaSetup | VarOffset: 0xD8 | Size: 0x1
1.0x: 0x0
0.1x: 0x1
0.01x: 0x2
0.001x: 0x3
PEG Port Configuration
PEG2 Physical Slot Number | VarStore: SaSetup | VarOffset: 0xE2 | Size: 0x2
Min: 0x0 | Max: 0x1FFF | Step: 0x1
PEG Port Configuration
PEG2 Hotplug | VarStore: SaSetup | VarOffset: 0xD4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
Extra Bus Reserved | VarStore: SaSetup | VarOffset: 0xE8 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PEG Port Configuration
Reseved Memory | VarStore: SaSetup | VarOffset: 0xED | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PEG Port Configuration
Reserved I/O | VarStore: SaSetup | VarOffset: 0xF1 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PEG Port Configuration
Enable Root Port | VarStore: SaSetup | VarOffset: 0x62 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Auto: 0x2
PEG Port Configuration
Max Link Speed | VarStore: SaSetup | VarOffset: 0x66 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PEG Port Configuration
Max Link Width | VarStore: SaSetup | VarOffset: 0x6A | Size: 0x1
Auto: 0x0
Force X1: 0x1
Force X2: 0x2
PEG Port Configuration
Power Down Unused Lanes | VarStore: SaSetup | VarOffset: 0x6E | Size: 0x1
Disabled: 0x0
Auto: 0x1
PEG Port Configuration
Gen3 Eq Phase 2 | VarStore: SaSetup | VarOffset: 0x7A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Auto: 0x2
PEG Port Configuration
Gen3 Eq Phase 3 Method | VarStore: SaSetup | VarOffset: 0x76 | Size: 0x1
Auto: 0x0
Adaptive Hardware Equalization: 0x1
Adaptive Software Equalization: 0x2
Static Equalization: 0x3
Disabled: 0x4
PEG Port Configuration
ASPM | VarStore: SaSetup | VarOffset: 0x5A | Size: 0x1
Disabled: 0x0
Auto: 0x4
ASPM L0s: 0x1
ASPM L1: 0x2
ASPM L0sL1: 0x3
PEG Port Configuration
ASPM L0s | VarStore: SaSetup | VarOffset: 0x5E | Size: 0x1
Root Port Only: 0x1
Endpoint Port Only: 0x2
Both Root and Endpoint Ports: 0x3
PEG Port Configuration
De-emphasis Control | VarStore: SaSetup | VarOffset: 0x7E | Size: 0x1
-6 dB: 0x0
-3.5 dB: 0x1
PEG Port Configuration
OBFF | VarStore: SaSetup | VarOffset: 0x8A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
LTR | VarStore: SaSetup | VarOffset: 0x86 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
PEG3 Slot Power Limit Value | VarStore: SaSetup | VarOffset: 0xDD | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
PEG Port Configuration
PEG3 Slot Power Limit Scale | VarStore: SaSetup | VarOffset: 0xD9 | Size: 0x1
1.0x: 0x0
0.1x: 0x1
0.01x: 0x2
0.001x: 0x3
PEG Port Configuration
PEG3 Physical Slot Number | VarStore: SaSetup | VarOffset: 0xE4 | Size: 0x2
Min: 0x0 | Max: 0x1FFF | Step: 0x1
PEG Port Configuration
PEG2 Hotplug | VarStore: SaSetup | VarOffset: 0xD5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
PEG0 Max Payload size | VarStore: SaSetup | VarOffset: 0x7F | Size: 0x1
Auto: 0xFF
128: 0x0
256 TLP: 0x1
PEG Port Configuration
PEG1 Max Payload size | VarStore: SaSetup | VarOffset: 0x80 | Size: 0x1
Auto: 0xFF
128: 0x0
256 TLP: 0x1
PEG Port Configuration
PEG2 Max Payload size | VarStore: SaSetup | VarOffset: 0x81 | Size: 0x1
Auto: 0xFF
128: 0x0
256 TLP: 0x1
PEG Port Configuration
PEG3 Max Payload size | VarStore: SaSetup | VarOffset: 0x82 | Size: 0x1
Auto: 0xFF
128: 0x0
256 TLP: 0x1
PEG Port Configuration
Program PCIe ASPM after OpROM | VarStore: SaSetup | VarOffset: 0xC7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
Program Static Phase1 Eq | VarStore: SaSetup | VarOffset: 0x8B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
Always Attempt SW EQ | VarStore: SaSetup | VarOffset: 0xC6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
Number of Presets to test | VarStore: SaSetup | VarOffset: 0xD1 | Size: 0x1
7, 3, 5, 8: 0x0
0 - 9: 0x1
Auto: 0x2
PEG Port Configuration
Allow PERST# GPIO Usage | VarStore: SaSetup | VarOffset: 0xC8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
SW EQ Enable VOC | VarStore: SaSetup | VarOffset: 0xCC | Size: 0x1
Jitter Only Test Mode: 0x0
Jitter & VOC Test Mode: 0x1
Auto: 0x2
PEG Port Configuration
Jitter Dwell Time | VarStore: SaSetup | VarOffset: 0xC4 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PEG Port Configuration
Jitter Error Target | VarStore: SaSetup | VarOffset: 0xC9 | Size: 0x2
Min: 0x1 | Max: 0xFFFF | Step: 0x1
PEG Port Configuration
VOC Dwell Time | VarStore: SaSetup | VarOffset: 0xCD | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PEG Port Configuration
VOC Error Target | VarStore: SaSetup | VarOffset: 0xCF | Size: 0x2
Min: 0x1 | Max: 0xFFFF | Step: 0x1
PEG Port Configuration
Generate BDAT PEG Margin Data | VarStore: SaSetup | VarOffset: 0xCB | Size: 0x1
Disabled: 0x0
Generate Port Jitter Data: 0x1
PEG Port Configuration
PEG IMR | VarStore: SaSetup | VarOffset: 0x275 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
PEG IMR Size | VarStore: SaSetup | VarOffset: 0x276 | Size: 0x2
Min: 0x0 | Max: 0x400 | Step: 0x1
PEG Port Configuration
RP index for IMR | VarStore: SaSetup | VarOffset: 0x278 | Size: 0x1
Min: 0x1 | Max: 0x4 | Step: 0x1
PEG Port Configuration
PCIe Rx CEM Test Mode | VarStore: SaSetup | VarOffset: 0x6F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
PEG Lane number for Test | VarStore: SaSetup | VarOffset: 0x70 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
PEG Port Configuration
Non-Protocol Awareness | VarStore: SaSetup | VarOffset: 0x71 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PEG Port Configuration
PCIe Spread Spectrum Clocking | VarStore: SaSetup | VarOffset: 0x72 | Size: 0x1
Enabled: 0x0
Disabled: 0x1
Gen3 Root Port Preset value for each Lane
Lane 0 | VarStore: SaSetup | VarOffset: 0x8C | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 1 | VarStore: SaSetup | VarOffset: 0x8D | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 2 | VarStore: SaSetup | VarOffset: 0x8E | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 3 | VarStore: SaSetup | VarOffset: 0x8F | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 4 | VarStore: SaSetup | VarOffset: 0x90 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 5 | VarStore: SaSetup | VarOffset: 0x91 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 6 | VarStore: SaSetup | VarOffset: 0x92 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 7 | VarStore: SaSetup | VarOffset: 0x93 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 8 | VarStore: SaSetup | VarOffset: 0x94 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 9 | VarStore: SaSetup | VarOffset: 0x95 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 10 | VarStore: SaSetup | VarOffset: 0x96 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 11 | VarStore: SaSetup | VarOffset: 0x97 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 12 | VarStore: SaSetup | VarOffset: 0x98 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 13 | VarStore: SaSetup | VarOffset: 0x99 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 14 | VarStore: SaSetup | VarOffset: 0x9A | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Root Port Preset value for each Lane
Lane 15 | VarStore: SaSetup | VarOffset: 0x9B | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 0 | VarStore: SaSetup | VarOffset: 0x9C | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 1 | VarStore: SaSetup | VarOffset: 0x9D | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 2 | VarStore: SaSetup | VarOffset: 0x9E | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 3 | VarStore: SaSetup | VarOffset: 0x9F | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 4 | VarStore: SaSetup | VarOffset: 0xA0 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 5 | VarStore: SaSetup | VarOffset: 0xA1 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 6 | VarStore: SaSetup | VarOffset: 0xA2 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 7 | VarStore: SaSetup | VarOffset: 0xA3 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 8 | VarStore: SaSetup | VarOffset: 0xA4 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 9 | VarStore: SaSetup | VarOffset: 0xA5 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 10 | VarStore: SaSetup | VarOffset: 0xA6 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 11 | VarStore: SaSetup | VarOffset: 0xA7 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 12 | VarStore: SaSetup | VarOffset: 0xA8 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 13 | VarStore: SaSetup | VarOffset: 0xA9 | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 14 | VarStore: SaSetup | VarOffset: 0xAA | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Preset value for each Lane
Lane 15 | VarStore: SaSetup | VarOffset: 0xAB | Size: 0x1
Min: 0x0 | Max: 0x9 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 0 | VarStore: SaSetup | VarOffset: 0xAC | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 1 | VarStore: SaSetup | VarOffset: 0xAD | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 2 | VarStore: SaSetup | VarOffset: 0xAE | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 3 | VarStore: SaSetup | VarOffset: 0xAF | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 4 | VarStore: SaSetup | VarOffset: 0xB0 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 5 | VarStore: SaSetup | VarOffset: 0xB1 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 6 | VarStore: SaSetup | VarOffset: 0xB2 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 7 | VarStore: SaSetup | VarOffset: 0xB3 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 8 | VarStore: SaSetup | VarOffset: 0xB4 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 9 | VarStore: SaSetup | VarOffset: 0xB5 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 10 | VarStore: SaSetup | VarOffset: 0xB6 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 11 | VarStore: SaSetup | VarOffset: 0xB7 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 12 | VarStore: SaSetup | VarOffset: 0xB8 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 13 | VarStore: SaSetup | VarOffset: 0xB9 | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 14 | VarStore: SaSetup | VarOffset: 0xBA | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 Endpoint Hint value for each Lane
Lane 15 | VarStore: SaSetup | VarOffset: 0xBB | Size: 0x1
Min: 0x0 | Max: 0x6 | Step: 0x1
Gen3 RxCTLE Control
Bundle0 | VarStore: SaSetup | VarOffset: 0xBC | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Gen3 RxCTLE Control
Bundle1 | VarStore: SaSetup | VarOffset: 0xBD | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Gen3 RxCTLE Control
Bundle2 | VarStore: SaSetup | VarOffset: 0xBE | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Gen3 RxCTLE Control
Bundle3 | VarStore: SaSetup | VarOffset: 0xBF | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Gen3 RxCTLE Control
Bundle4 | VarStore: SaSetup | VarOffset: 0xC0 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Gen3 RxCTLE Control
Bundle5 | VarStore: SaSetup | VarOffset: 0xC1 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Gen3 RxCTLE Control
Bundle6 | VarStore: SaSetup | VarOffset: 0xC2 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Gen3 RxCTLE Control
Bundle7 | VarStore: SaSetup | VarOffset: 0xC3 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Gen3 RxCTLE Control
PEG10 RxCTLE Override | VarStore: SaSetup | VarOffset: 0x26F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Gen3 RxCTLE Control
PEG11 RxCTLE Override | VarStore: SaSetup | VarOffset: 0x270 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Gen3 RxCTLE Control
PEG12 RxCTLE Override | VarStore: SaSetup | VarOffset: 0x271 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Gen3 RxCTLE Control
PEG60 RxCTLE Override | VarStore: SaSetup | VarOffset: 0x272 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Gen3 RxCTLE Control
DMI RxCTLE Override | VarStore: SaSetup | VarOffset: 0x273 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
LCD Control
Primary IGFX Boot Display | VarStore: SaSetup | VarOffset: 0x3A | Size: 0x1
VBIOS Default: 0x0
EFP: 0x4
LFP: 0x8
EFP3: 0x20
EFP2: 0x40
EFP4: 0x10
LCD Control
Secondary IGFX Boot Display | VarStore: SaSetup | VarOffset: 0x3B | Size: 0x1
Disabled: 0x0
EFP: 0x4
EFP3: 0x20
EFP2: 0x40
EFP4: 0x10
LCD Control
LCD Panel Type | VarStore: SaSetup | VarOffset: 0x3C | Size: 0x1
VBIOS Default: 0x0
640x480 LVDS: 0x1
800x600 LVDS: 0x2
1024x768 LVDS: 0x3
1280x1024 LVDS: 0x4
1400x1050 LVDS1: 0x5
1400x1050 LVDS2: 0x6
1600x1200 LVDS: 0x7
1280x768 LVDS: 0x8
1680x1050 LVDS: 0x9
1920x1200 LVDS: 0xA
1600x900 LVDS: 0xD
1280x800 LVDS: 0xE
1280x600 LVDS: 0xF
2048x1536 LVDS: 0x10
1366x768 LVDS: 0x11
LCD Control
Panel Scaling | VarStore: SaSetup | VarOffset: 0x3D | Size: 0x1
Auto: 0x0
Off: 0x1
Force Scaling: 0x6
LCD Control
Backlight Control | VarStore: SaSetup | VarOffset: 0x3F | Size: 0x1
PWM Inverted: 0x0
PWM Normal: 0x2
LCD Control
Active LFP | VarStore: SaSetup | VarOffset: 0x41 | Size: 0x1
No eDP: 0x0
eDP Port-A: 0x3
LCD Control
Panel Color Depth | VarStore: SaSetup | VarOffset: 0x42 | Size: 0x1
18 Bit: 0x0
24 Bit: 0x1
LCD Control
Backlight Brightness | VarStore: SaSetup | VarOffset: 0x4D | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Intel(R) Ultrabook Event Support
IUER Slate Enable | VarStore: SaSetup | VarOffset: 0x240 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Ultrabook Event Support
Slate Mode boot value | VarStore: SaSetup | VarOffset: 0x23B | Size: 0x1
Slate Mode: 0x0
Laptop Mode: 0x1
Intel(R) Ultrabook Event Support
Slate Mode on S3 and S4 resume | VarStore: SaSetup | VarOffset: 0x23C | Size: 0x1
No change: 0x0
Toggle: 0x1
Intel(R) Ultrabook Event Support
IUER Dock Enable | VarStore: SaSetup | VarOffset: 0x241 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Intel(R) Ultrabook Event Support
Dock Mode boot value | VarStore: SaSetup | VarOffset: 0x23D | Size: 0x1
Undocked: 0x0
Docked: 0x1
Intel(R) Ultrabook Event Support
Dock Mode upon S3 and S4 resume | VarStore: SaSetup | VarOffset: 0x23E | Size: 0x1
No change: 0x0
Toggle: 0x1
GT - Power Management Control
RC6(Render Standby) | VarStore: SaSetup | VarOffset: 0x3E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
GT - Power Management Control
Maximum GT Frequency | VarStore: SaSetup | VarOffset: 0x50 | Size: 0x1
Default Max Frequency: 0xFF
100Mhz: 0x2
150Mhz: 0x3
200Mhz: 0x4
250Mhz: 0x5
300Mhz: 0x6
350Mhz: 0x7
400Mhz: 0x8
450Mhz: 0x9
500Mhz: 0xA
550Mhz: 0xB
600Mhz: 0xC
650Mhz: 0xD
700Mhz: 0xE
750Mhz: 0xF
800Mhz: 0x10
850Mhz: 0x11
900Mhz: 0x12
950Mhz: 0x13
1000Mhz: 0x14
1050Mhz: 0x15
1100Mhz: 0x16
1150Mhz: 0x17
1200Mhz: 0x18
GT - Power Management Control
Disable Turbo GT Frequency | VarStore: SaSetup | VarOffset: 0x51 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Memory Training Algorithms
Early Command Training | VarStore: SaSetup | VarOffset: 0x1B0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
SenseAmp Offset Training | VarStore: SaSetup | VarOffset: 0x1B1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Early ReadMPR Timing Centering 2D | VarStore: SaSetup | VarOffset: 0x1B2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Read MPR Training | VarStore: SaSetup | VarOffset: 0x1B3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Receive Enable Training | VarStore: SaSetup | VarOffset: 0x1B4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Jedec Write Leveling | VarStore: SaSetup | VarOffset: 0x1B5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
LPDDR4 Write DQ DQS Retraining | VarStore: SaSetup | VarOffset: 0x233 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Early Write Time Centering 2D | VarStore: SaSetup | VarOffset: 0x1B6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Early Read Time Centering 2D | VarStore: SaSetup | VarOffset: 0x1B7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Write Timing Centering 1D | VarStore: SaSetup | VarOffset: 0x1B8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Write Voltage Centering 1D | VarStore: SaSetup | VarOffset: 0x1B9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Read Timing Centering 1D | VarStore: SaSetup | VarOffset: 0x1BA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Dimm ODT Training* | VarStore: SaSetup | VarOffset: 0x1BB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
DIMM RON Training* | VarStore: SaSetup | VarOffset: 0x1BC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Write Drive Strength/Equalization 2D* | VarStore: SaSetup | VarOffset: 0x1BD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Write Slew Rate Training* | VarStore: SaSetup | VarOffset: 0x1BE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Read ODT Training* | VarStore: SaSetup | VarOffset: 0x1BF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Read Equalization Training* | VarStore: SaSetup | VarOffset: 0x1C0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Read Amplifier Training* | VarStore: SaSetup | VarOffset: 0x1C1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Write Timing Centering 2D | VarStore: SaSetup | VarOffset: 0x1C2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Read Timing Centering 2D | VarStore: SaSetup | VarOffset: 0x1C3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Command Voltage Centering | VarStore: SaSetup | VarOffset: 0x1C6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Write Voltage Centering 2D | VarStore: SaSetup | VarOffset: 0x1C4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Read Voltage Centering 2D | VarStore: SaSetup | VarOffset: 0x1C5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Late Command Training | VarStore: SaSetup | VarOffset: 0x1C7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Round Trip Latency | VarStore: SaSetup | VarOffset: 0x1C8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Turn Around Timing Training | VarStore: SaSetup | VarOffset: 0x1C9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Rank Margin Tool | VarStore: SaSetup | VarOffset: 0x1CA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Margin Check Limit | VarStore: SaSetup | VarOffset: 0x1AD | Size: 0x1
Disabled: 0x0
L1: 0x1
L2: 0x2
Both: 0x3
Memory Training Algorithms
Margin Limit Check L2 | VarStore: SaSetup | VarOffset: 0x1AE | Size: 0x2
Min: 0x1 | Max: 0x12C | Step: 0x1
Memory Training Algorithms
Memory Test | VarStore: SaSetup | VarOffset: 0x1CB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
DIMM SPD Alias Test | VarStore: SaSetup | VarOffset: 0x1CC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Receive Enable Centering 1D | VarStore: SaSetup | VarOffset: 0x1CD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Retrain Margin Check | VarStore: SaSetup | VarOffset: 0x1CE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Write Drive Strength Up/Dn independently | VarStore: SaSetup | VarOffset: 0x1CF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Command Drive Strength and Equalization | VarStore: SaSetup | VarOffset: 0x1D0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Command Normalization | VarStore: SaSetup | VarOffset: 0x1D1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Early DQ Write Drive Strength and Equalization Training | VarStore: SaSetup | VarOffset: 0x1D2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Read Voltage Centering 1D | VarStore: SaSetup | VarOffset: 0x1D3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Dimm ODT CA Training | VarStore: SaSetup | VarOffset: 0x1D4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
Duty Cycle Correction | VarStore: SaSetup | VarOffset: 0x1D5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Training Algorithms
DQ DFE Training | VarStore: SaSetup | VarOffset: 0x1D6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Thermal Configuration
Memory Thermal Management | VarStore: SaSetup | VarOffset: 0x229 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Thermal Configuration
PECI Injected Temperature | VarStore: SaSetup | VarOffset: 0x22A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Thermal Configuration
EXTTS# via TS-on-Board | VarStore: SaSetup | VarOffset: 0x22B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Thermal Configuration
EXTTS# via TS-on-DIMM | VarStore: SaSetup | VarOffset: 0x22C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Power and Thermal Throttling
DDR PowerDown and idle counter | VarStore: SaSetup | VarOffset: 0x1EA | Size: 0x1
PCODE: 0x0
BIOS: 0x1
Memory Power and Thermal Throttling
For LPDDR Only: DDR PowerDown and idle counter | VarStore: SaSetup | VarOffset: 0x1EB | Size: 0x1
PCODE: 0x0
BIOS: 0x1
Memory Power and Thermal Throttling
REFRESH_2X_MODE | VarStore: SaSetup | VarOffset: 0x1EC | Size: 0x1
Disabled: 0x0
1- Enabled for WARM or HOT: 0x1
2- Enabled HOT only: 0x2
Memory Power and Thermal Throttling
LPDDR Thermal Sensor | VarStore: SaSetup | VarOffset: 0x1ED | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Power and Thermal Throttling
SelfRefresh Enable | VarStore: SaSetup | VarOffset: 0x222 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Power and Thermal Throttling
SelfRefresh IdleTimer | VarStore: SaSetup | VarOffset: 0x223 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Memory Power and Thermal Throttling
Throttler CKEMin Defeature | VarStore: SaSetup | VarOffset: 0x225 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Memory Power and Thermal Throttling
Throttler CKEMin Timer | VarStore: SaSetup | VarOffset: 0x226 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Power and Thermal Throttling
For LPDDR Only: Throttler CKEMin Defeature | VarStore: SaSetup | VarOffset: 0x227 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Memory Power and Thermal Throttling
For LPDDR Only: Throttler CKEMin Timer | VarStore: SaSetup | VarOffset: 0x228 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Dram Power Meter
Use user provided power weights, scale factor, and channel power floor values | VarStore: SaSetup | VarOffset: 0x1EF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Dram Power Meter
Energy Scale Factor | VarStore: SaSetup | VarOffset: 0x1F0 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Dram Power Meter
Idle Energy Ch0Dimm0 | VarStore: SaSetup | VarOffset: 0x20F | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Dram Power Meter
PowerDown Energy Ch0Dimm0 | VarStore: SaSetup | VarOffset: 0x211 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Dram Power Meter
Activate Energy Ch0Dimm0 | VarStore: SaSetup | VarOffset: 0x213 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Dram Power Meter
Read Energy Ch0Dimm0 | VarStore: SaSetup | VarOffset: 0x215 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Dram Power Meter
Write Energy Ch0Dimm0 | VarStore: SaSetup | VarOffset: 0x217 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Dram Power Meter
Idle Energy Ch0Dimm1 | VarStore: SaSetup | VarOffset: 0x20E | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Dram Power Meter
PowerDown Energy Ch0Dimm1 | VarStore: SaSetup | VarOffset: 0x210 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Dram Power Meter
Activate Energy Ch0Dimm1 | VarStore: SaSetup | VarOffset: 0x212 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Dram Power Meter
Read Energy Ch0Dimm1 | VarStore: SaSetup | VarOffset: 0x214 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Dram Power Meter
Write Energy Ch0Dimm1 | VarStore: SaSetup | VarOffset: 0x216 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Dram Power Meter
Idle Energy Ch1Dimm0 | VarStore: SaSetup | VarOffset: 0x219 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Dram Power Meter
PowerDown Energy Ch1Dimm0 | VarStore: SaSetup | VarOffset: 0x21B | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Dram Power Meter
Activate Energy Ch1Dimm0 | VarStore: SaSetup | VarOffset: 0x21D | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Dram Power Meter
Read Energy Ch1Dimm0 | VarStore: SaSetup | VarOffset: 0x21F | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Dram Power Meter
Write Energy Ch1Dimm0 | VarStore: SaSetup | VarOffset: 0x221 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Dram Power Meter
Idle Energy Ch1Dimm1 | VarStore: SaSetup | VarOffset: 0x218 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Dram Power Meter
PowerDown Energy Ch1Dimm1 | VarStore: SaSetup | VarOffset: 0x21A | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
Dram Power Meter
Activate Energy Ch1Dimm1 | VarStore: SaSetup | VarOffset: 0x21C | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Dram Power Meter
Read Energy Ch1Dimm1 | VarStore: SaSetup | VarOffset: 0x21E | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Dram Power Meter
Write Energy Ch1Dimm1 | VarStore: SaSetup | VarOffset: 0x220 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Lock Thermal Management Registers | VarStore: SaSetup | VarOffset: 0x1EE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Thermal Reporting
Extern Therm Status | VarStore: SaSetup | VarOffset: 0x1E7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Thermal Reporting
Closed Loop Therm Manage | VarStore: SaSetup | VarOffset: 0x1E8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Thermal Reporting
Open Loop Therm Manage | VarStore: SaSetup | VarOffset: 0x1E9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory Thermal Reporting
Warm Threshold Ch0 Dimm0 | VarStore: SaSetup | VarOffset: 0x1FE | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Warm Threshold Ch0 Dimm1 | VarStore: SaSetup | VarOffset: 0x1FF | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Hot Threshold Ch0 Dimm0 | VarStore: SaSetup | VarOffset: 0x202 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Hot Threshold Ch0 Dimm1 | VarStore: SaSetup | VarOffset: 0x203 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Warm Threshold Ch1 Dimm0 | VarStore: SaSetup | VarOffset: 0x200 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Warm Threshold Ch1 Dimm1 | VarStore: SaSetup | VarOffset: 0x201 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Hot Threshold Ch1 Dimm0 | VarStore: SaSetup | VarOffset: 0x204 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Hot Threshold Ch1 Dimm1 | VarStore: SaSetup | VarOffset: 0x205 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Warm Budget Ch0 Dimm0 | VarStore: SaSetup | VarOffset: 0x206 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Warm Budget Ch0 Dimm1 | VarStore: SaSetup | VarOffset: 0x207 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Hot Budget Ch0 Dimm0 | VarStore: SaSetup | VarOffset: 0x20A | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Hot Budget Ch0 Dimm1 | VarStore: SaSetup | VarOffset: 0x20B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Warm Budget Ch1 Dimm0 | VarStore: SaSetup | VarOffset: 0x208 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Warm Budget Ch1 Dimm1 | VarStore: SaSetup | VarOffset: 0x209 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Hot Budget Ch1 Dimm0 | VarStore: SaSetup | VarOffset: 0x20C | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory Thermal Reporting
Hot Budget Ch1 Dimm1 | VarStore: SaSetup | VarOffset: 0x20D | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory RAPL
Rapl Power Floor Ch0 | VarStore: SaSetup | VarOffset: 0x1F2 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory RAPL
Rapl Power Floor Ch1 | VarStore: SaSetup | VarOffset: 0x1F1 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x1
Memory RAPL
RAPL PL Lock | VarStore: SaSetup | VarOffset: 0x1F3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory RAPL
RAPL PL 1 enable | VarStore: SaSetup | VarOffset: 0x1FB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory RAPL
RAPL PL 1 Power | VarStore: SaSetup | VarOffset: 0x1FC | Size: 0x2
Min: 0x0 | Max: 0x3FFF | Step: 0x1
Memory RAPL
RAPL PL 1 WindowX | VarStore: SaSetup | VarOffset: 0x1F9 | Size: 0x1
Min: 0x0 | Max: 0x3 | Step: 0x1
Memory RAPL
RAPL PL 1 WindowY | VarStore: SaSetup | VarOffset: 0x1FA | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Memory RAPL
RAPL PL 2 enable | VarStore: SaSetup | VarOffset: 0x1F6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Memory RAPL
RAPL PL 2 Power | VarStore: SaSetup | VarOffset: 0x1F7 | Size: 0x2
Min: 0x0 | Max: 0x3FFF | Step: 0x1
Memory RAPL
RAPL PL 2 WindowX | VarStore: SaSetup | VarOffset: 0x1F4 | Size: 0x1
Min: 0x0 | Max: 0x3 | Step: 0x1
Memory RAPL
RAPL PL 2 WindowY | VarStore: SaSetup | VarOffset: 0x1F5 | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
MIPI Camera Configuration
Control Logic 1 | VarStore: Setup | VarOffset: 0x6A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
MIPI Camera Configuration
Control Logic 2 | VarStore: Setup | VarOffset: 0x6B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
MIPI Camera Configuration
Control Logic 3 | VarStore: Setup | VarOffset: 0x6C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
MIPI Camera Configuration
Control Logic 4 | VarStore: Setup | VarOffset: 0x6D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
MIPI Camera Configuration
Camera1 | VarStore: Setup | VarOffset: 0x6E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
MIPI Camera Configuration
Camera2 | VarStore: Setup | VarOffset: 0x6F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
MIPI Camera Configuration
Camera3 | VarStore: Setup | VarOffset: 0x70 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
MIPI Camera Configuration
Camera4 | VarStore: Setup | VarOffset: 0x71 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Link options
Sensor Model | VarStore: Setup | VarOffset: 0x10F | Size: 0x1
OV16860: 0xE
OV8856: 0xD
OV9234: 0xC
IMX135: 0x0
OV5693: 0x1
IMX179: 0x2
OV8858: 0x3
OV2740-IVCAM: 0x4
OV9728: 0x5
IMX188: 0x6
IMX208: 0x7
OV5670: 0x8
OV8865: 0x9
HM2051: 0xA
OV2742: 0xB
User Custom: 0xFF
Link options
Custom HID
Link options
Lanes Clock division | VarStore: Setup | VarOffset: 0x72 | Size: 0x1
4 4 2 2: 0x0
4 4 3 1: 0x2
4 4 4 0: 0x3
8 0 2 2: 0x4
8 0 3 1: 0x6
8 0 4 0: 0x7
Link options
CRD Version | VarStore: Setup | VarOffset: 0x16A | Size: 0x1
PTC: 0x10
CRD-D: 0x20
CRD-G: 0x30
Kilshon-PPV: 0x40
CRD-G2: 0x50
Link options
GPIO control | VarStore: Setup | VarOffset: 0x176 | Size: 0x1
No Control Logic: 0xFF
Control Logic 1: 0x0
Control Logic 2: 0x1
Control Logic 3: 0x2
Control Logic 4: 0x3
Link options
Camera position | VarStore: Setup | VarOffset: 0x122 | Size: 0x1
Front: 0x61
Back: 0x69
Link options
Flash Support | VarStore: Setup | VarOffset: 0x177 | Size: 0x1
Driver default: 0x0
Disabled: 0x2
Enabled: 0x3
Link options
Privacy LED | VarStore: Setup | VarOffset: 0x178 | Size: 0x1
Driver default: 0x0
ILEDA, 16mA: 0x1
ILEDB, 2mA: 0x2
ILEDB, 4mA: 0x3
ILEDB, 8mA: 0x4
ILEDB, 16mA: 0x5
Link options
Rotation | VarStore: Setup | VarOffset: 0x179 | Size: 0x1
0: 0x0
90: 0x2
180: 0x4
270: 0x6
Link options
PMIC Position | VarStore: Setup | VarOffset: 0x17A | Size: 0x1
Position 1: 0x0
Position 2: 0x1
Link options
Voltage Rail | VarStore: Setup | VarOffset: 0x17B | Size: 0x1
3 voltage rail: 0x0
2 voltage rail: 0x1
Link options
Camera module name
Link options
LaneUsed | VarStore: Setup | VarOffset: 0x16B | Size: 0x1
x1: 0x1
x2: 0x2
x3: 0x3
x4: 0x4
x8: 0x8
Link options
MCLK | VarStore: Setup | VarOffset: 0x172 | Size: 0x4
Min: 0x5B8D80 | Max: 0x19BFCC0 | Step: 0x186A0
Link options
EEPROM Type | VarStore: Setup | VarOffset: 0x16C | Size: 0x1
ROM_NONE: 0x0
ROM_OTP: 0x1
ROM_EEPROM_16K_64: 0x2
ROM_EEPROM_16K_16: 0x3
ROM_OTP_ACPI_ACPI: 0x4
ROM_ACPI: 0x5
ROM_EEPROM_BRCA016GWZ: 0x6
ROM_EEPROM_24AA32: 0x7
ROM_EEPROM_CAT24C08: 0x8
ROM_EEPROM_M24C64: 0x9
ROM_EEPROM_DW9806B: 0xA
Link options
VCM Type | VarStore: Setup | VarOffset: 0x16D | Size: 0x1
VCM_NONE: 0x0
VCM_AD5823: 0x1
VCM_DW9714: 0x2
VCM_AD5816: 0x3
VCM_DW9719: 0x4
VCM_DW9718: 0x5
VCM_DW9806B: 0x6
VCM_WV517S: 0x7
VCM_LC898122XA: 0x8
VCM_LC898212AXB: 0x9
VCM_RESERVED1: 0xA
VCM_RESERVED2: 0xB
Link options
Number of I2C Components | VarStore: Setup | VarOffset: 0x143 | Size: 0x1
Min: 0x0 | Max: 0xC | Step: 0x1
Link options
I2C Channel | VarStore: Setup | VarOffset: 0x144 | Size: 0x1
I2C0: 0x0
I2C1: 0x1
I2C2: 0x2
I2C3: 0x3
I2C4: 0x4
I2C5: 0x5
Link options
I2C Address | VarStore: Setup | VarOffset: 0x145 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x15D | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x147 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x15E | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x149 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x15F | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x14B | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x160 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x14D | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x161 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x14F | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x162 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x151 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x163 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x153 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x164 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x155 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x165 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x157 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x166 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x159 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x167 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x15B | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x168 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
Sensor Model | VarStore: Setup | VarOffset: 0x17C | Size: 0x1
OV16860: 0xE
OV8856: 0xD
OV9234: 0xC
IMX135: 0x0
OV5693: 0x1
IMX179: 0x2
OV8858: 0x3
OV2740-IVCAM: 0x4
OV9728: 0x5
IMX188: 0x6
IMX208: 0x7
OV5670: 0x8
OV8865: 0x9
HM2051: 0xA
OV2742: 0xB
User Custom: 0xFF
Link options
Custom HID
Link options
Lanes Clock division | VarStore: Setup | VarOffset: 0x72 | Size: 0x1
4 4 2 2: 0x0
4 4 3 1: 0x2
4 4 4 0: 0x3
8 0 2 2: 0x4
8 0 3 1: 0x6
8 0 4 0: 0x7
Link options
CRD Version | VarStore: Setup | VarOffset: 0x1D7 | Size: 0x1
PTC: 0x10
CRD-D: 0x20
CRD-G: 0x30
Kilshon-PPV: 0x40
CRD-G2: 0x50
Link options
GPIO control | VarStore: Setup | VarOffset: 0x1E3 | Size: 0x1
No Control Logic: 0xFF
Control Logic 1: 0x0
Control Logic 2: 0x1
Control Logic 3: 0x2
Control Logic 4: 0x3
Link options
Camera position | VarStore: Setup | VarOffset: 0x18F | Size: 0x1
Front: 0x61
Back: 0x69
Link options
Flash Support | VarStore: Setup | VarOffset: 0x1E4 | Size: 0x1
Driver default: 0x0
Disabled: 0x2
Enabled: 0x3
Link options
Privacy LED | VarStore: Setup | VarOffset: 0x1E5 | Size: 0x1
Driver default: 0x0
ILEDA, 16mA: 0x1
ILEDB, 2mA: 0x2
ILEDB, 4mA: 0x3
ILEDB, 8mA: 0x4
ILEDB, 16mA: 0x5
Link options
Rotation | VarStore: Setup | VarOffset: 0x1E6 | Size: 0x1
0: 0x0
90: 0x2
180: 0x4
270: 0x6
Link options
PMIC Position | VarStore: Setup | VarOffset: 0x1E7 | Size: 0x1
Position 1: 0x0
Position 2: 0x1
Link options
Voltage Rail | VarStore: Setup | VarOffset: 0x1E8 | Size: 0x1
3 voltage rail: 0x0
2 voltage rail: 0x1
Link options
Camera module name
Link options
LaneUsed | VarStore: Setup | VarOffset: 0x1D8 | Size: 0x1
x1: 0x1
x2: 0x2
x3: 0x3
x4: 0x4
Link options
MCLK | VarStore: Setup | VarOffset: 0x1DF | Size: 0x4
Min: 0x5B8D80 | Max: 0x19BFCC0 | Step: 0x186A0
Link options
EEPROM Type | VarStore: Setup | VarOffset: 0x1D9 | Size: 0x1
ROM_NONE: 0x0
ROM_OTP: 0x1
ROM_EEPROM_16K_64: 0x2
ROM_EEPROM_16K_16: 0x3
ROM_OTP_ACPI_ACPI: 0x4
ROM_ACPI: 0x5
ROM_EEPROM_BRCA016GWZ: 0x6
ROM_EEPROM_24AA32: 0x7
ROM_EEPROM_CAT24C08: 0x8
ROM_EEPROM_M24C64: 0x9
ROM_EEPROM_DW9806B: 0xA
Link options
VCM Type | VarStore: Setup | VarOffset: 0x1DA | Size: 0x1
VCM_NONE: 0x0
VCM_AD5823: 0x1
VCM_DW9714: 0x2
VCM_AD5816: 0x3
VCM_DW9719: 0x4
VCM_DW9718: 0x5
VCM_DW9806B: 0x6
VCM_WV517S: 0x7
VCM_LC898122XA: 0x8
VCM_LC898212AXB: 0x9
VCM_RESERVED1: 0xA
VCM_RESERVED2: 0xB
Link options
Number of I2C Components | VarStore: Setup | VarOffset: 0x1B0 | Size: 0x1
Min: 0x0 | Max: 0xC | Step: 0x1
Link options
I2C Channel | VarStore: Setup | VarOffset: 0x1B1 | Size: 0x1
I2C0: 0x0
I2C1: 0x1
I2C2: 0x2
I2C3: 0x3
I2C4: 0x4
I2C5: 0x5
Link options
I2C Address | VarStore: Setup | VarOffset: 0x1B2 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x1CA | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x1B4 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x1CB | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x1B6 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x1CC | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x1B8 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x1CD | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x1BA | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x1CE | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x1BC | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x1CF | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x1BE | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x1D0 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x1C0 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x1D1 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x1C2 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x1D2 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x1C4 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x1D3 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x1C6 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x1D4 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x1C8 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x1D5 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
Sensor Model | VarStore: Setup | VarOffset: 0x1E9 | Size: 0x1
OV16860: 0xE
OV8856: 0xD
OV9234: 0xC
IMX135: 0x0
OV5693: 0x1
IMX179: 0x2
OV8858: 0x3
OV2740-IVCAM: 0x4
OV9728: 0x5
IMX188: 0x6
IMX208: 0x7
OV5670: 0x8
OV8865: 0x9
HM2051: 0xA
OV2742: 0xB
User Custom: 0xFF
Link options
Custom HID
Link options
Lanes Clock division | VarStore: Setup | VarOffset: 0x72 | Size: 0x1
4 4 2 2: 0x0
4 4 3 1: 0x2
4 4 4 0: 0x3
8 0 2 2: 0x4
8 0 3 1: 0x6
8 0 4 0: 0x7
Link options
CRD Version | VarStore: Setup | VarOffset: 0x244 | Size: 0x1
PTC: 0x10
CRD-D: 0x20
CRD-G: 0x30
Kilshon-PPV: 0x40
CRD-G2: 0x50
Link options
GPIO control | VarStore: Setup | VarOffset: 0x250 | Size: 0x1
No Control Logic: 0xFF
Control Logic 1: 0x0
Control Logic 2: 0x1
Control Logic 3: 0x2
Control Logic 4: 0x3
Link options
Camera position | VarStore: Setup | VarOffset: 0x1FC | Size: 0x1
Front: 0x61
Back: 0x69
Link options
Flash Support | VarStore: Setup | VarOffset: 0x251 | Size: 0x1
Driver default: 0x0
Disabled: 0x2
Enabled: 0x3
Link options
Privacy LED | VarStore: Setup | VarOffset: 0x252 | Size: 0x1
Driver default: 0x0
ILEDA, 16mA: 0x1
ILEDB, 2mA: 0x2
ILEDB, 4mA: 0x3
ILEDB, 8mA: 0x4
ILEDB, 16mA: 0x5
Link options
Rotation | VarStore: Setup | VarOffset: 0x253 | Size: 0x1
0: 0x0
90: 0x2
180: 0x4
270: 0x6
Link options
PMIC Position | VarStore: Setup | VarOffset: 0x254 | Size: 0x1
Position 1: 0x0
Position 2: 0x1
Link options
Voltage Rail | VarStore: Setup | VarOffset: 0x255 | Size: 0x1
3 voltage rail: 0x0
2 voltage rail: 0x1
Link options
Camera module name
Link options
LaneUsed | VarStore: Setup | VarOffset: 0x245 | Size: 0x1
x1: 0x1
x2: 0x2
x3: 0x3
x4: 0x4
Link options
MCLK | VarStore: Setup | VarOffset: 0x24C | Size: 0x4
Min: 0x5B8D80 | Max: 0x19BFCC0 | Step: 0x186A0
Link options
EEPROM Type | VarStore: Setup | VarOffset: 0x246 | Size: 0x1
ROM_NONE: 0x0
ROM_OTP: 0x1
ROM_EEPROM_16K_64: 0x2
ROM_EEPROM_16K_16: 0x3
ROM_OTP_ACPI_ACPI: 0x4
ROM_ACPI: 0x5
ROM_EEPROM_BRCA016GWZ: 0x6
ROM_EEPROM_24AA32: 0x7
ROM_EEPROM_CAT24C08: 0x8
ROM_EEPROM_M24C64: 0x9
ROM_EEPROM_DW9806B: 0xA
Link options
VCM Type | VarStore: Setup | VarOffset: 0x247 | Size: 0x1
VCM_NONE: 0x0
VCM_AD5823: 0x1
VCM_DW9714: 0x2
VCM_AD5816: 0x3
VCM_DW9719: 0x4
VCM_DW9718: 0x5
VCM_DW9806B: 0x6
VCM_WV517S: 0x7
VCM_LC898122XA: 0x8
VCM_LC898212AXB: 0x9
VCM_RESERVED1: 0xA
VCM_RESERVED2: 0xB
Link options
Number of I2C Components | VarStore: Setup | VarOffset: 0x21D | Size: 0x1
Min: 0x0 | Max: 0xC | Step: 0x1
Link options
I2C Channel | VarStore: Setup | VarOffset: 0x21E | Size: 0x1
I2C0: 0x0
I2C1: 0x1
I2C2: 0x2
I2C3: 0x3
I2C4: 0x4
I2C5: 0x5
Link options
I2C Address | VarStore: Setup | VarOffset: 0x21F | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x237 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x221 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x238 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x223 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x239 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x225 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x23A | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x227 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x23B | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x229 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x23C | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x22B | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x23D | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x22D | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x23E | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x22F | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x23F | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x231 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x240 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x233 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x241 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x235 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x242 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
Sensor Model | VarStore: Setup | VarOffset: 0x256 | Size: 0x1
OV16860: 0xE
OV8856: 0xD
OV9234: 0xC
IMX135: 0x0
OV5693: 0x1
IMX179: 0x2
OV8858: 0x3
OV2740-IVCAM: 0x4
OV9728: 0x5
IMX188: 0x6
IMX208: 0x7
OV5670: 0x8
OV8865: 0x9
HM2051: 0xA
OV2742: 0xB
User Custom: 0xFF
Link options
Custom HID
Link options
Lanes Clock division | VarStore: Setup | VarOffset: 0x72 | Size: 0x1
4 4 2 2: 0x0
4 4 3 1: 0x2
4 4 4 0: 0x3
8 0 2 2: 0x4
8 0 3 1: 0x6
8 0 4 0: 0x7
Link options
CRD Version | VarStore: Setup | VarOffset: 0x2B1 | Size: 0x1
PTC: 0x10
CRD-D: 0x20
CRD-G: 0x30
Kilshon-PPV: 0x40
CRD-G2: 0x50
Link options
GPIO control | VarStore: Setup | VarOffset: 0x2BD | Size: 0x1
No Control Logic: 0xFF
Control Logic 1: 0x0
Control Logic 2: 0x1
Control Logic 3: 0x2
Control Logic 4: 0x3
Link options
Camera position | VarStore: Setup | VarOffset: 0x269 | Size: 0x1
Front: 0x61
Back: 0x69
Link options
Flash Support | VarStore: Setup | VarOffset: 0x2BE | Size: 0x1
Driver default: 0x0
Disabled: 0x2
Enabled: 0x3
Link options
Privacy LED | VarStore: Setup | VarOffset: 0x2BF | Size: 0x1
Driver default: 0x0
ILEDA, 16mA: 0x1
ILEDB, 2mA: 0x2
ILEDB, 4mA: 0x3
ILEDB, 8mA: 0x4
ILEDB, 16mA: 0x5
Link options
Rotation | VarStore: Setup | VarOffset: 0x2C0 | Size: 0x1
0: 0x0
90: 0x2
180: 0x4
270: 0x6
Link options
PMIC Position | VarStore: Setup | VarOffset: 0x2C1 | Size: 0x1
Position 1: 0x0
Position 2: 0x1
Link options
Voltage Rail | VarStore: Setup | VarOffset: 0x2C2 | Size: 0x1
3 voltage rail: 0x0
2 voltage rail: 0x1
Link options
Camera module name
Link options
LaneUsed | VarStore: Setup | VarOffset: 0x2B2 | Size: 0x1
x1: 0x1
x2: 0x2
x3: 0x3
x4: 0x4
Link options
MCLK | VarStore: Setup | VarOffset: 0x2B9 | Size: 0x4
Min: 0x5B8D80 | Max: 0x19BFCC0 | Step: 0x186A0
Link options
EEPROM Type | VarStore: Setup | VarOffset: 0x2B3 | Size: 0x1
ROM_NONE: 0x0
ROM_OTP: 0x1
ROM_EEPROM_16K_64: 0x2
ROM_EEPROM_16K_16: 0x3
ROM_OTP_ACPI_ACPI: 0x4
ROM_ACPI: 0x5
ROM_EEPROM_BRCA016GWZ: 0x6
ROM_EEPROM_24AA32: 0x7
ROM_EEPROM_CAT24C08: 0x8
ROM_EEPROM_M24C64: 0x9
ROM_EEPROM_DW9806B: 0xA
Link options
VCM Type | VarStore: Setup | VarOffset: 0x2B4 | Size: 0x1
VCM_NONE: 0x0
VCM_AD5823: 0x1
VCM_DW9714: 0x2
VCM_AD5816: 0x3
VCM_DW9719: 0x4
VCM_DW9718: 0x5
VCM_DW9806B: 0x6
VCM_WV517S: 0x7
VCM_LC898122XA: 0x8
VCM_LC898212AXB: 0x9
VCM_RESERVED1: 0xA
VCM_RESERVED2: 0xB
Link options
Number of I2C Components | VarStore: Setup | VarOffset: 0x28A | Size: 0x1
Min: 0x0 | Max: 0xC | Step: 0x1
Link options
I2C Channel | VarStore: Setup | VarOffset: 0x28B | Size: 0x1
I2C0: 0x0
I2C1: 0x1
I2C2: 0x2
I2C3: 0x3
I2C4: 0x4
I2C5: 0x5
Link options
I2C Address | VarStore: Setup | VarOffset: 0x28C | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x2A4 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x28E | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x2A5 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x290 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x2A6 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x292 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x2A7 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x294 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x2A8 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x296 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x2A9 | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x298 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x2AA | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x29A | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x2AB | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x29C | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x2AC | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x29E | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x2AD | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x2A0 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x2AE | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Link options
I2C Address | VarStore: Setup | VarOffset: 0x2A2 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Link options
Device Type | VarStore: Setup | VarOffset: 0x2AF | Size: 0x1
Sensor: 0x0
VCM: 0x1
EEPROM: 0x2
EEPROM_EXT1: 0x3
EEPROM_EXT2: 0x4
EEPROM_EXT3: 0x5
EEPROM_EXT4: 0x6
EEPROM_EXT5: 0x7
EEPROM_EXT6: 0x8
EEPROM_EXT7: 0x9
IO Expander: 0xA
Flash: 0xC
Control Logic options
Control Logic Type | VarStore: Setup | VarOffset: 0x73 | Size: 0x1
Discrete: 0x1
PMIC_TPS68470: 0x2
PMIC_UP6641: 0x3
PMIC_USER0: 0xFD
PMIC_USER1: 0xFE
Control Logic options
CRD Version | VarStore: Setup | VarOffset: 0x74 | Size: 0x1
PTC: 0x10
CRD-D: 0x20
CRD-G: 0x30
Kilshon-PPV: 0x40
CRD-G2: 0x50
Control Logic options
Input Clock | VarStore: Setup | VarOffset: 0x75 | Size: 0x4
20 MHz: 0x10
24 MHz: 0x20
26 MHz: 0x30
19.2 MHz: 0x40
Control Logic options
PCH Clock Source | VarStore: Setup | VarOffset: 0x79 | Size: 0x1
IMGCLKOUT_0: 0x0
IMGCLKOUT_1: 0x1
Control Logic options
PMIC Flash Panel | VarStore: Setup | VarOffset: 0x7E | Size: 0x1
Front: 0x21
Back: 0x29
Control Logic options
I2C Channel | VarStore: Setup | VarOffset: 0x7B | Size: 0x1
I2C0: 0x0
I2C1: 0x1
I2C2: 0x2
I2C3: 0x3
I2C4: 0x4
I2C5: 0x5
Control Logic options
I2C Address | VarStore: Setup | VarOffset: 0x7C | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Control Logic options
WLED1 Type | VarStore: Setup | VarOffset: 0x84 | Size: 0x1
Disabled: 0x0
White Led: 0x1
Warm Led: 0x2
IR Led: 0x3
Xeon Led: 0x4
Control Logic options
WLED1 Flash Max Current | VarStore: Setup | VarOffset: 0x7F | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Control Logic options
WLED1 Torch Max Current | VarStore: Setup | VarOffset: 0x80 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Control Logic options
WLED2 Type | VarStore: Setup | VarOffset: 0x85 | Size: 0x1
Disabled: 0x0
White Led: 0x1
Warm Led: 0x2
IR Led: 0x3
Xeon Led: 0x4
Control Logic options
WLED2 Flash Max Current | VarStore: Setup | VarOffset: 0x81 | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Control Logic options
WLED2 Torch Max Current | VarStore: Setup | VarOffset: 0x82 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Control Logic options
SubPlatformId | VarStore: Setup | VarOffset: 0x83 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Control Logic options
Number of GPIO Pins | VarStore: Setup | VarOffset: 0x7A | Size: 0x1
Min: 0x0 | Max: 0x4 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0x86 | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0x8A | Size: 0x1
A: 0x0
B: 0x1
C: 0x2
D: 0x3
E: 0x4
F: 0x5
G: 0x6
H: 0x7
Control Logic options
Function | VarStore: Setup | VarOffset: 0x8E | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0x92 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0x96 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0x87 | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0x8B | Size: 0x1
A: 0x0
B: 0x1
C: 0x2
D: 0x3
E: 0x4
F: 0x5
G: 0x6
H: 0x7
Control Logic options
Function | VarStore: Setup | VarOffset: 0x8F | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0x93 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0x97 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0x88 | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0x8C | Size: 0x1
A: 0x0
B: 0x1
C: 0x2
D: 0x3
E: 0x4
F: 0x5
G: 0x6
H: 0x7
Control Logic options
Function | VarStore: Setup | VarOffset: 0x90 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0x94 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0x98 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0x89 | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0x8D | Size: 0x1
A: 0x0
B: 0x1
C: 0x2
D: 0x3
E: 0x4
F: 0x5
G: 0x6
H: 0x7
Control Logic options
Function | VarStore: Setup | VarOffset: 0x91 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0x95 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0x99 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Control Logic Type | VarStore: Setup | VarOffset: 0x9A | Size: 0x1
Discrete: 0x1
PMIC_TPS68470: 0x2
PMIC_UP6641: 0x3
PMIC_USER0: 0xFD
PMIC_USER1: 0xFE
Control Logic options
CRD Version | VarStore: Setup | VarOffset: 0x9B | Size: 0x1
PTC: 0x10
CRD-D: 0x20
CRD-G: 0x30
Kilshon-PPV: 0x40
CRD-G2: 0x50
Control Logic options
Input Clock | VarStore: Setup | VarOffset: 0x9C | Size: 0x4
20 MHz: 0x10
24 MHz: 0x20
26 MHz: 0x30
19.2 MHz: 0x40
Control Logic options
PCH Clock Source | VarStore: Setup | VarOffset: 0xA0 | Size: 0x1
IMGCLKOUT_0: 0x0
IMGCLKOUT_1: 0x1
Control Logic options
PMIC Flash Panel | VarStore: Setup | VarOffset: 0xA5 | Size: 0x1
Front: 0x21
Back: 0x29
Control Logic options
I2C Channel | VarStore: Setup | VarOffset: 0xA2 | Size: 0x1
I2C0: 0x0
I2C1: 0x1
I2C2: 0x2
I2C3: 0x3
I2C4: 0x4
I2C5: 0x5
Control Logic options
I2C Address | VarStore: Setup | VarOffset: 0xA3 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Control Logic options
WLED1 Type | VarStore: Setup | VarOffset: 0xAB | Size: 0x1
Disabled: 0x0
White Led: 0x1
Warm Led: 0x2
IR Led: 0x3
Xeon Led: 0x4
Control Logic options
WLED1 Flash Max Current | VarStore: Setup | VarOffset: 0xA6 | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Control Logic options
WLED1 Torch Max Current | VarStore: Setup | VarOffset: 0xA7 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Control Logic options
WLED2 Type | VarStore: Setup | VarOffset: 0xAC | Size: 0x1
Disabled: 0x0
White Led: 0x1
Warm Led: 0x2
IR Led: 0x3
Xeon Led: 0x4
Control Logic options
WLED2 Flash Max Current | VarStore: Setup | VarOffset: 0xA8 | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Control Logic options
WLED2 Torch Max Current | VarStore: Setup | VarOffset: 0xA9 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Control Logic options
SubPlatformId | VarStore: Setup | VarOffset: 0xAA | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Control Logic options
Number of GPIO Pins | VarStore: Setup | VarOffset: 0xA1 | Size: 0x1
Min: 0x0 | Max: 0x4 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0xAD | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0xB1 | Size: 0x1
A: 0x0
B: 0x1
C: 0x2
D: 0x3
E: 0x4
F: 0x5
G: 0x6
H: 0x7
Control Logic options
Function | VarStore: Setup | VarOffset: 0xB5 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0xB9 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0xBD | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0xAE | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0xB2 | Size: 0x1
A: 0x0
B: 0x1
C: 0x2
D: 0x3
E: 0x4
F: 0x5
G: 0x6
H: 0x7
Control Logic options
Function | VarStore: Setup | VarOffset: 0xB6 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0xBA | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0xBE | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0xAF | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0xB3 | Size: 0x1
A: 0x0
B: 0x1
C: 0x2
D: 0x3
E: 0x4
F: 0x5
G: 0x6
H: 0x7
Control Logic options
Function | VarStore: Setup | VarOffset: 0xB7 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0xBB | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0xBF | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0xB0 | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0xB4 | Size: 0x1
A: 0x0
B: 0x1
C: 0x2
D: 0x3
E: 0x4
F: 0x5
G: 0x6
H: 0x7
Control Logic options
Function | VarStore: Setup | VarOffset: 0xB8 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0xBC | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0xC0 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Control Logic Type | VarStore: Setup | VarOffset: 0xC1 | Size: 0x1
Discrete: 0x1
PMIC_TPS68470: 0x2
PMIC_UP6641: 0x3
PMIC_USER0: 0xFD
PMIC_USER1: 0xFE
Control Logic options
CRD Version | VarStore: Setup | VarOffset: 0xC2 | Size: 0x1
PTC: 0x10
CRD-D: 0x20
CRD-G: 0x30
Kilshon-PPV: 0x40
CRD-G2: 0x50
Control Logic options
Input Clock | VarStore: Setup | VarOffset: 0xC3 | Size: 0x4
20 MHz: 0x10
24 MHz: 0x20
26 MHz: 0x30
19.2 MHz: 0x40
Control Logic options
PCH Clock Source | VarStore: Setup | VarOffset: 0xC7 | Size: 0x1
IMGCLKOUT_0: 0x0
IMGCLKOUT_1: 0x1
Control Logic options
PMIC Flash Panel | VarStore: Setup | VarOffset: 0xCC | Size: 0x1
Front: 0x21
Back: 0x29
Control Logic options
I2C Channel | VarStore: Setup | VarOffset: 0xC9 | Size: 0x1
I2C0: 0x0
I2C1: 0x1
I2C2: 0x2
I2C3: 0x3
I2C4: 0x4
I2C5: 0x5
Control Logic options
I2C Address | VarStore: Setup | VarOffset: 0xCA | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Control Logic options
WLED1 Type | VarStore: Setup | VarOffset: 0xD2 | Size: 0x1
Disabled: 0x0
White Led: 0x1
Warm Led: 0x2
IR Led: 0x3
Xeon Led: 0x4
Control Logic options
WLED1 Flash Max Current | VarStore: Setup | VarOffset: 0xCD | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Control Logic options
WLED1 Torch Max Current | VarStore: Setup | VarOffset: 0xCE | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Control Logic options
WLED2 Type | VarStore: Setup | VarOffset: 0xD3 | Size: 0x1
Disabled: 0x0
White Led: 0x1
Warm Led: 0x2
IR Led: 0x3
Xeon Led: 0x4
Control Logic options
WLED2 Flash Max Current | VarStore: Setup | VarOffset: 0xCF | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Control Logic options
WLED2 Torch Max Current | VarStore: Setup | VarOffset: 0xD0 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Control Logic options
SubPlatformId | VarStore: Setup | VarOffset: 0xD1 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Control Logic options
Number of GPIO Pins | VarStore: Setup | VarOffset: 0xC8 | Size: 0x1
Min: 0x0 | Max: 0x4 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0xD4 | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0xD8 | Size: 0x1
A: 0x0
B: 0x1
C: 0x2
D: 0x3
E: 0x4
F: 0x5
G: 0x6
H: 0x7
Control Logic options
Function | VarStore: Setup | VarOffset: 0xDC | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0xE0 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0xE4 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0xD5 | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0xD9 | Size: 0x1
A: 0x0
B: 0x1
C: 0x2
D: 0x3
E: 0x4
F: 0x5
G: 0x6
H: 0x7
Control Logic options
Function | VarStore: Setup | VarOffset: 0xDD | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0xE1 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0xE5 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0xD6 | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0xDA | Size: 0x1
A: 0x0
B: 0x1
C: 0x2
D: 0x3
E: 0x4
F: 0x5
G: 0x6
H: 0x7
Control Logic options
Function | VarStore: Setup | VarOffset: 0xDE | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0xE2 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0xE6 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0xD7 | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0xDB | Size: 0x1
A: 0x0
B: 0x1
C: 0x2
D: 0x3
E: 0x4
F: 0x5
G: 0x6
H: 0x7
Control Logic options
Function | VarStore: Setup | VarOffset: 0xDF | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0xE3 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0xE7 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Control Logic Type | VarStore: Setup | VarOffset: 0xE8 | Size: 0x1
Discrete: 0x1
PMIC_TPS68470: 0x2
PMIC_UP6641: 0x3
PMIC_USER0: 0xFD
PMIC_USER1: 0xFE
Control Logic options
CRD Version | VarStore: Setup | VarOffset: 0xE9 | Size: 0x1
PTC: 0x10
CRD-D: 0x20
CRD-G: 0x30
Kilshon-PPV: 0x40
CRD-G2: 0x50
Control Logic options
Input Clock | VarStore: Setup | VarOffset: 0xEA | Size: 0x4
20 MHz: 0x10
24 MHz: 0x20
26 MHz: 0x30
19.2 MHz: 0x40
Control Logic options
PCH Clock Source | VarStore: Setup | VarOffset: 0xEE | Size: 0x1
IMGCLKOUT_0: 0x0
IMGCLKOUT_1: 0x1
Control Logic options
PMIC Flash Panel | VarStore: Setup | VarOffset: 0xF3 | Size: 0x1
Front: 0x21
Back: 0x29
Control Logic options
I2C Channel | VarStore: Setup | VarOffset: 0xF0 | Size: 0x1
I2C0: 0x0
I2C1: 0x1
I2C2: 0x2
I2C3: 0x3
I2C4: 0x4
I2C5: 0x5
Control Logic options
I2C Address | VarStore: Setup | VarOffset: 0xF1 | Size: 0x2
Min: 0x0 | Max: 0x7F | Step: 0x1
Control Logic options
WLED1 Type | VarStore: Setup | VarOffset: 0xF9 | Size: 0x1
Disabled: 0x0
White Led: 0x1
Warm Led: 0x2
IR Led: 0x3
Xeon Led: 0x4
Control Logic options
WLED1 Flash Max Current | VarStore: Setup | VarOffset: 0xF4 | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Control Logic options
WLED1 Torch Max Current | VarStore: Setup | VarOffset: 0xF5 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Control Logic options
WLED2 Type | VarStore: Setup | VarOffset: 0xFA | Size: 0x1
Disabled: 0x0
White Led: 0x1
Warm Led: 0x2
IR Led: 0x3
Xeon Led: 0x4
Control Logic options
WLED2 Flash Max Current | VarStore: Setup | VarOffset: 0xF6 | Size: 0x1
Min: 0x0 | Max: 0x1F | Step: 0x1
Control Logic options
WLED2 Torch Max Current | VarStore: Setup | VarOffset: 0xF7 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
Control Logic options
SubPlatformId | VarStore: Setup | VarOffset: 0xF8 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x1
Control Logic options
Number of GPIO Pins | VarStore: Setup | VarOffset: 0xEF | Size: 0x1
Min: 0x0 | Max: 0x4 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0xFB | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0xFF | Size: 0x1
A: 0x0
B: 0x1
C: 0x2
D: 0x3
E: 0x4
F: 0x5
G: 0x6
H: 0x7
Control Logic options
Function | VarStore: Setup | VarOffset: 0x103 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0x107 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0x10B | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0xFC | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0x100 | Size: 0x1
A: 0x0
B: 0x1
C: 0x2
D: 0x3
E: 0x4
F: 0x5
G: 0x6
H: 0x7
Control Logic options
Function | VarStore: Setup | VarOffset: 0x104 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0x108 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0x10C | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0xFD | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0x101 | Size: 0x1
A: 0x0
B: 0x1
C: 0x2
D: 0x3
E: 0x4
F: 0x5
G: 0x6
H: 0x7
Control Logic options
Function | VarStore: Setup | VarOffset: 0x105 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0x109 | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0x10D | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Group Pad Number | VarStore: Setup | VarOffset: 0xFE | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
Control Logic options
Group Number | VarStore: Setup | VarOffset: 0x102 | Size: 0x1
A: 0x0
B: 0x1
C: 0x2
D: 0x3
E: 0x4
F: 0x5
G: 0x6
H: 0x7
Control Logic options
Function | VarStore: Setup | VarOffset: 0x106 | Size: 0x1
Reset: 0x0
Power_En: 0xB
Clock_En: 0xC
pLED_En: 0xD
Control Logic options
Active Value | VarStore: Setup | VarOffset: 0x10A | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
Control Logic options
Initial Value | VarStore: Setup | VarOffset: 0x10E | Size: 0x1
Min: 0x0 | Max: 0x1 | Step: 0x1
PCI Express Configuration
PCI Express Clock Gating | VarStore: SaSetup | VarOffset: 0x2A5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
Fia Programming | VarStore: SaSetup | VarOffset: 0x2A4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
PCI Express Power Gating | VarStore: SaSetup | VarOffset: 0x2A6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
Set SRL | VarStore: SaSetup | VarOffset: 0x2A9 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
PCI Express Configuration
Compliance Test Mode | VarStore: SaSetup | VarOffset: 0x2A7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
PCIe function swap | VarStore: SaSetup | VarOffset: 0x2A8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
CDR Relock for PEG60 | VarStore: SaSetup | VarOffset: 0x4FB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
New FOM for PEG60 | VarStore: SaSetup | VarOffset: 0x502 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
Error Flag Reset Assertion for PEG60 | VarStore: SaSetup | VarOffset: 0x508 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
CDR Relock for PEG10 | VarStore: SaSetup | VarOffset: 0x4FC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
New FOM for PEG10 | VarStore: SaSetup | VarOffset: 0x503 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
Error Flag Reset Assertion for PEG10 | VarStore: SaSetup | VarOffset: 0x509 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
Manual Ana Save Restore for PEG60 | VarStore: SaSetup | VarOffset: 0x50E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
Manual Ana Save Restore for PEG10 | VarStore: SaSetup | VarOffset: 0x50F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
Assertion on Link Down GPIOs | VarStore: SaSetup | VarOffset: 0x2DB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
Enable ClockReq Messaging | VarStore: SaSetup | VarOffset: 0x2DC | Size: 0x1
Enabled: 0x1
Disabled: 0x0
PCI Express Gen3 Eq Lanes
PCIE1 Cm | VarStore: SaSetup | VarOffset: 0x284 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE1 Cp | VarStore: SaSetup | VarOffset: 0x294 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE2 Cm | VarStore: SaSetup | VarOffset: 0x285 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE2 Cp | VarStore: SaSetup | VarOffset: 0x295 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE3 Cm | VarStore: SaSetup | VarOffset: 0x286 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE3 Cp | VarStore: SaSetup | VarOffset: 0x296 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE4 Cm | VarStore: SaSetup | VarOffset: 0x287 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE4 Cp | VarStore: SaSetup | VarOffset: 0x297 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE5 Cm | VarStore: SaSetup | VarOffset: 0x288 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE5 Cp | VarStore: SaSetup | VarOffset: 0x298 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE6 Cm | VarStore: SaSetup | VarOffset: 0x289 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE6 Cp | VarStore: SaSetup | VarOffset: 0x299 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE7 Cm | VarStore: SaSetup | VarOffset: 0x28A | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE7 Cp | VarStore: SaSetup | VarOffset: 0x29A | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE8 Cm | VarStore: SaSetup | VarOffset: 0x28B | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE8 Cp | VarStore: SaSetup | VarOffset: 0x29B | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE9 Cm | VarStore: SaSetup | VarOffset: 0x28C | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE9 Cp | VarStore: SaSetup | VarOffset: 0x29C | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE10 Cm | VarStore: SaSetup | VarOffset: 0x28D | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE10 Cp | VarStore: SaSetup | VarOffset: 0x29D | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE11 Cm | VarStore: SaSetup | VarOffset: 0x28E | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE11 Cp | VarStore: SaSetup | VarOffset: 0x29E | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE12 Cm | VarStore: SaSetup | VarOffset: 0x28F | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE12 Cp | VarStore: SaSetup | VarOffset: 0x29F | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE13 Cm | VarStore: SaSetup | VarOffset: 0x290 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE13 Cp | VarStore: SaSetup | VarOffset: 0x2A0 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE14 Cm | VarStore: SaSetup | VarOffset: 0x291 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE14 Cp | VarStore: SaSetup | VarOffset: 0x2A1 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE15 Cm | VarStore: SaSetup | VarOffset: 0x292 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE15 Cp | VarStore: SaSetup | VarOffset: 0x2A2 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE16 Cm | VarStore: SaSetup | VarOffset: 0x293 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE16 Cp | VarStore: SaSetup | VarOffset: 0x2A3 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Root Port 1
Enable Root Port | VarStore: SaSetup | VarOffset: 0x280 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
Connection Type | VarStore: SaSetup | VarOffset: 0x2E1 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 1
L1 Substates | VarStore: SaSetup | VarOffset: 0x329 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 1
Gen3 Eq Phase3 Method | VarStore: SaSetup | VarOffset: 0x31D | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 1
Gen4 Eq Phase3 Method | VarStore: SaSetup | VarOffset: 0x321 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 1
ACS | VarStore: SaSetup | VarOffset: 0x2ED | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
PTM | VarStore: SaSetup | VarOffset: 0x33D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
DPC | VarStore: SaSetup | VarOffset: 0x311 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
VC | VarStore: SaSetup | VarOffset: 0x349 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
Multi-VC | VarStore: SaSetup | VarOffset: 0x34D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
EDPC | VarStore: SaSetup | VarOffset: 0x315 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
URR | VarStore: SaSetup | VarOffset: 0x2F5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
FER | VarStore: SaSetup | VarOffset: 0x2F9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
NFER | VarStore: SaSetup | VarOffset: 0x2FD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
CER | VarStore: SaSetup | VarOffset: 0x301 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
CTO | VarStore: PchSetup | VarOffset: 0x186 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
SEFE | VarStore: SaSetup | VarOffset: 0x305 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
SENFE | VarStore: SaSetup | VarOffset: 0x309 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
SECE | VarStore: SaSetup | VarOffset: 0x30D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
PME SCI | VarStore: SaSetup | VarOffset: 0x2E5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
Hot Plug | VarStore: SaSetup | VarOffset: 0x2DD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
Advanced Error Reporting | VarStore: SaSetup | VarOffset: 0x2F1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
Max Link Speed | VarStore: SaSetup | VarOffset: 0x319 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 1
Transmitter Half Swing | VarStore: SaSetup | VarOffset: 0x2E9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
Detect Timeout | VarStore: SaSetup | VarOffset: 0x341 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 1
LTR | VarStore: SaSetup | VarOffset: 0x356 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
Snoop Latency Override | VarStore: SaSetup | VarOffset: 0x35E | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 1
Snoop Latency Value | VarStore: SaSetup | VarOffset: 0x366 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 1
Snoop Latency Multiplier | VarStore: SaSetup | VarOffset: 0x362 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 1
Non Snoop Latency Override | VarStore: SaSetup | VarOffset: 0x36E | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 1
Non Snoop Latency Value | VarStore: SaSetup | VarOffset: 0x376 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 1
Non Snoop Latency Multiplier | VarStore: SaSetup | VarOffset: 0x372 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 1
Force LTR Override | VarStore: SaSetup | VarOffset: 0x37E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
LTR Lock | VarStore: SaSetup | VarOffset: 0x35A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
Override HW EQ settings | VarStore: SaSetup | VarOffset: 0x382 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 1
Coeff0 Cm | VarStore: SaSetup | VarOffset: 0x383 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Root Port 1
Coeff0 Cp | VarStore: SaSetup | VarOffset: 0x388 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Root Port 1
Coeff1 Cm | VarStore: SaSetup | VarOffset: 0x384 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Root Port 1
Coeff1 Cp | VarStore: SaSetup | VarOffset: 0x389 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Root Port 1
Coeff2 Cm | VarStore: SaSetup | VarOffset: 0x385 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Root Port 1
Coeff2 Cp | VarStore: SaSetup | VarOffset: 0x38A | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Root Port 1
Coeff3 Cm | VarStore: SaSetup | VarOffset: 0x386 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Root Port 1
Coeff3 Cp | VarStore: SaSetup | VarOffset: 0x38B | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Root Port 1
Coeff4 Cm | VarStore: SaSetup | VarOffset: 0x387 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Root Port 1
Coeff4 Cp | VarStore: SaSetup | VarOffset: 0x38C | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Root Port 1
UPTP | VarStore: SaSetup | VarOffset: 0x32D | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 1
DPTP | VarStore: SaSetup | VarOffset: 0x331 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 1
Coeff0 Cm | VarStore: SaSetup | VarOffset: 0x38D | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Root Port 1
Coeff0 Cp | VarStore: SaSetup | VarOffset: 0x392 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Root Port 1
Coeff1 Cm | VarStore: SaSetup | VarOffset: 0x38E | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Root Port 1
Coeff1 Cp | VarStore: SaSetup | VarOffset: 0x393 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Root Port 1
Coeff2 Cm | VarStore: SaSetup | VarOffset: 0x38F | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Root Port 1
Coeff2 Cp | VarStore: SaSetup | VarOffset: 0x394 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Root Port 1
Coeff3 Cm | VarStore: SaSetup | VarOffset: 0x390 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Root Port 1
Coeff3 Cp | VarStore: SaSetup | VarOffset: 0x395 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Root Port 1
Coeff4 Cm | VarStore: SaSetup | VarOffset: 0x391 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Root Port 1
Coeff4 Cp | VarStore: SaSetup | VarOffset: 0x396 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Root Port 1
UPTP | VarStore: SaSetup | VarOffset: 0x335 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 1
DPTP | VarStore: SaSetup | VarOffset: 0x339 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 2
Enable Root Port | VarStore: SaSetup | VarOffset: 0x281 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
Connection Type | VarStore: SaSetup | VarOffset: 0x2E2 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 2
L1 Substates | VarStore: SaSetup | VarOffset: 0x32A | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 2
Gen3 Eq Phase3 Method | VarStore: SaSetup | VarOffset: 0x31E | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 2
Gen4 Eq Phase3 Method | VarStore: SaSetup | VarOffset: 0x322 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 2
ACS | VarStore: SaSetup | VarOffset: 0x2EE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
PTM | VarStore: SaSetup | VarOffset: 0x33E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
DPC | VarStore: SaSetup | VarOffset: 0x312 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
VC | VarStore: SaSetup | VarOffset: 0x34A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
Multi-VC | VarStore: SaSetup | VarOffset: 0x34E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
EDPC | VarStore: SaSetup | VarOffset: 0x316 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
URR | VarStore: SaSetup | VarOffset: 0x2F6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
FER | VarStore: SaSetup | VarOffset: 0x2FA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
NFER | VarStore: SaSetup | VarOffset: 0x2FE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
CER | VarStore: SaSetup | VarOffset: 0x302 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
CTO | VarStore: PchSetup | VarOffset: 0x187 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
SEFE | VarStore: SaSetup | VarOffset: 0x306 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
SENFE | VarStore: SaSetup | VarOffset: 0x30A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
SECE | VarStore: SaSetup | VarOffset: 0x30E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
PME SCI | VarStore: SaSetup | VarOffset: 0x2E6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
Hot Plug | VarStore: SaSetup | VarOffset: 0x2DE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
Advanced Error Reporting | VarStore: SaSetup | VarOffset: 0x2F2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
Max Link Speed | VarStore: SaSetup | VarOffset: 0x31A | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 2
Transmitter Half Swing | VarStore: SaSetup | VarOffset: 0x2EA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
Detect Timeout | VarStore: SaSetup | VarOffset: 0x343 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 2
LTR | VarStore: SaSetup | VarOffset: 0x357 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
Snoop Latency Override | VarStore: SaSetup | VarOffset: 0x35F | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 2
Snoop Latency Value | VarStore: SaSetup | VarOffset: 0x368 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 2
Snoop Latency Multiplier | VarStore: SaSetup | VarOffset: 0x363 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 2
Non Snoop Latency Override | VarStore: SaSetup | VarOffset: 0x36F | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 2
Non Snoop Latency Value | VarStore: SaSetup | VarOffset: 0x378 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 2
Non Snoop Latency Multiplier | VarStore: SaSetup | VarOffset: 0x373 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 2
Force LTR Override | VarStore: SaSetup | VarOffset: 0x37F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
LTR Lock | VarStore: SaSetup | VarOffset: 0x35B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
UPTP | VarStore: SaSetup | VarOffset: 0x32E | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 2
DPTP | VarStore: SaSetup | VarOffset: 0x332 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 2
UPTP | VarStore: SaSetup | VarOffset: 0x336 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 2
DPTP | VarStore: SaSetup | VarOffset: 0x33A | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 3
Enable Root Port | VarStore: SaSetup | VarOffset: 0x282 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
Connection Type | VarStore: SaSetup | VarOffset: 0x2E3 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 3
L1 Substates | VarStore: SaSetup | VarOffset: 0x32B | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 3
Gen3 Eq Phase3 Method | VarStore: SaSetup | VarOffset: 0x31F | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 3
Gen4 Eq Phase3 Method | VarStore: SaSetup | VarOffset: 0x323 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 3
ACS | VarStore: SaSetup | VarOffset: 0x2EF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
PTM | VarStore: SaSetup | VarOffset: 0x33F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
DPC | VarStore: SaSetup | VarOffset: 0x313 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
VC | VarStore: SaSetup | VarOffset: 0x34B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
Multi-VC | VarStore: SaSetup | VarOffset: 0x34F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
EDPC | VarStore: SaSetup | VarOffset: 0x317 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
URR | VarStore: SaSetup | VarOffset: 0x2F7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
FER | VarStore: SaSetup | VarOffset: 0x2FB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
NFER | VarStore: SaSetup | VarOffset: 0x2FF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
CER | VarStore: SaSetup | VarOffset: 0x303 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
CTO | VarStore: PchSetup | VarOffset: 0x188 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
SEFE | VarStore: SaSetup | VarOffset: 0x307 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
SENFE | VarStore: SaSetup | VarOffset: 0x30B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
SECE | VarStore: SaSetup | VarOffset: 0x30F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
PME SCI | VarStore: SaSetup | VarOffset: 0x2E7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
Hot Plug | VarStore: SaSetup | VarOffset: 0x2DF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
Advanced Error Reporting | VarStore: SaSetup | VarOffset: 0x2F3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
Max Link Speed | VarStore: SaSetup | VarOffset: 0x31B | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 3
Transmitter Half Swing | VarStore: SaSetup | VarOffset: 0x2EB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
Detect Timeout | VarStore: SaSetup | VarOffset: 0x345 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 3
LTR | VarStore: SaSetup | VarOffset: 0x358 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
Snoop Latency Override | VarStore: SaSetup | VarOffset: 0x360 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 3
Snoop Latency Value | VarStore: SaSetup | VarOffset: 0x36A | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 3
Snoop Latency Multiplier | VarStore: SaSetup | VarOffset: 0x364 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 3
Non Snoop Latency Override | VarStore: SaSetup | VarOffset: 0x370 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 3
Non Snoop Latency Value | VarStore: SaSetup | VarOffset: 0x37A | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 3
Non Snoop Latency Multiplier | VarStore: SaSetup | VarOffset: 0x374 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 3
Force LTR Override | VarStore: SaSetup | VarOffset: 0x380 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
LTR Lock | VarStore: SaSetup | VarOffset: 0x35C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
UPTP | VarStore: SaSetup | VarOffset: 0x32F | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 3
DPTP | VarStore: SaSetup | VarOffset: 0x333 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 3
UPTP | VarStore: SaSetup | VarOffset: 0x337 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 3
DPTP | VarStore: SaSetup | VarOffset: 0x33B | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 4
PCI Express Root Port 4 | VarStore: SaSetup | VarOffset: 0x283 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
Connection Type | VarStore: SaSetup | VarOffset: 0x2E4 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 4
L1 Substates | VarStore: SaSetup | VarOffset: 0x32C | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 4
Gen3 Eq Phase3 Method | VarStore: SaSetup | VarOffset: 0x320 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 4
Gen4 Eq Phase3 Method | VarStore: SaSetup | VarOffset: 0x324 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 4
ACS | VarStore: SaSetup | VarOffset: 0x2F0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
PTM | VarStore: SaSetup | VarOffset: 0x340 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
DPC | VarStore: SaSetup | VarOffset: 0x314 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
VC | VarStore: SaSetup | VarOffset: 0x34C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
Multi-VC | VarStore: SaSetup | VarOffset: 0x350 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
EDPC | VarStore: SaSetup | VarOffset: 0x318 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
URR | VarStore: SaSetup | VarOffset: 0x2F8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
FER | VarStore: SaSetup | VarOffset: 0x2FC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
NFER | VarStore: SaSetup | VarOffset: 0x300 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
CER | VarStore: SaSetup | VarOffset: 0x304 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
CTO | VarStore: PchSetup | VarOffset: 0x189 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
SEFE | VarStore: SaSetup | VarOffset: 0x308 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
SENFE | VarStore: SaSetup | VarOffset: 0x30C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
SECE | VarStore: SaSetup | VarOffset: 0x310 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
PME SCI | VarStore: SaSetup | VarOffset: 0x2E8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
Hot Plug | VarStore: SaSetup | VarOffset: 0x2E0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
Advanced Error Reporting | VarStore: SaSetup | VarOffset: 0x2F4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
PCIe Speed | VarStore: SaSetup | VarOffset: 0x31C | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 4
Transmitter Half Swing | VarStore: SaSetup | VarOffset: 0x2EC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
Detect Timeout | VarStore: SaSetup | VarOffset: 0x347 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 4
LTR | VarStore: SaSetup | VarOffset: 0x359 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
Snoop Latency Override | VarStore: SaSetup | VarOffset: 0x361 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 4
Snoop Latency Value | VarStore: SaSetup | VarOffset: 0x36C | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 4
Snoop Latency Multiplier | VarStore: SaSetup | VarOffset: 0x365 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 4
Non Snoop Latency Override | VarStore: SaSetup | VarOffset: 0x371 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 4
Non Snoop Latency Value | VarStore: SaSetup | VarOffset: 0x37C | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 4
Non Snoop Latency Multiplier | VarStore: SaSetup | VarOffset: 0x375 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 4
Force LTR Override | VarStore: SaSetup | VarOffset: 0x381 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
LTR Lock | VarStore: SaSetup | VarOffset: 0x35D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
UPTP | VarStore: SaSetup | VarOffset: 0x330 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 4
DPTP | VarStore: SaSetup | VarOffset: 0x334 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 4
UPTP | VarStore: SaSetup | VarOffset: 0x338 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 4
DPTP | VarStore: SaSetup | VarOffset: 0x33C | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCH-IO Configuration
PCH LAN Controller | VarStore: PchSetup | VarOffset: 0x9 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
PCH-IO Configuration
LAN Wake From DeepSx | VarStore: PchSetup | VarOffset: 0x5 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
PCH-IO Configuration
Wake On LAN Enable | VarStore: PchSetup | VarOffset: 0xC | Size: 0x1
Enabled: 0x1
Disabled: 0x0
PCH-IO Configuration
SLP_LAN# Low on DC Power | VarStore: PchSetup | VarOffset: 0xD | Size: 0x1
Enabled: 0x1
Disabled: 0x0
PCH-IO Configuration
Disqualify GBE Disconnect And ModPhy PG | VarStore: PchSetup | VarOffset: 0x6E4 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
PCH-IO Configuration
Sensor Hub Type | VarStore: Setup | VarOffset: 0x60 | Size: 0x1
None: 0x0
I2C Sensor Hub: 0x1
USB Sensor Hub: 0x2
PCH-IO Configuration
DeepSx Power Policies | VarStore: PchSetup | VarOffset: 0x4 | Size: 0x1
Disabled: 0x0
Enabled in S4-S5/Battery: 0x3
Enabled In S4-S5: 0x4
PCH-IO Configuration
PS_ON Enable | VarStore: PchSetup | VarOffset: 0x19 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
PCH-IO Configuration
Wake on WLAN and BT Enable | VarStore: PchSetup | VarOffset: 0xE | Size: 0x1
Enabled: 0x1
Disabled: 0x0
PCH-IO Configuration
DeepSx Wake on WLAN and BT Enable | VarStore: PchSetup | VarOffset: 0xF | Size: 0x1
Enabled: 0x1
Disabled: 0x0
PCH-IO Configuration
Disable DSX ACPRESENT PullDown | VarStore: PchSetup | VarOffset: 0x6 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
PCH-IO Configuration
CLKRUN# logic | VarStore: PchSetup | VarOffset: 0x10 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
Serial IRQ Mode | VarStore: PchSetup | VarOffset: 0x1E | Size: 0x1
Quiet: 0x0
Continuous: 0x1
PCH-IO Configuration
High Precision Event Timer | VarStore: PchSetup | VarOffset: 0x1A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
State After G3 | VarStore: PchSetup | VarOffset: 0x1B | Size: 0x1
S0 State: 0x0
S5 State: 0x1
PCH-IO Configuration
Port 80h Redirection | VarStore: PchSetup | VarOffset: 0x1C | Size: 0x1
LPC Bus: 0x0
PCIE Bus: 0x1
PCH-IO Configuration
Enhance Port 80h LPC Decoding | VarStore: PchSetup | VarOffset: 0x1D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
Compatible Revision ID | VarStore: PchSetup | VarOffset: 0x15 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
Legacy IO Low Latency | VarStore: PchSetup | VarOffset: 0x6E9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
PCH Cross Throttling | VarStore: PchSetup | VarOffset: 0x67D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
PCH Energy Reporting | VarStore: PchSetup | VarOffset: 0x11 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
Enable TCO Timer | VarStore: PchSetup | VarOffset: 0x14 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
PCIe PLL SSC | VarStore: PchSetup | VarOffset: 0x1F | Size: 0x1
Enabled: 0xFF
Disabled: 0x0
PCH-IO Configuration
IOAPIC 24-119 Entries | VarStore: PchSetup | VarOffset: 0x67C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
Enable 8254 Clock Gate | VarStore: PchSetup | VarOffset: 0x6E6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Enabled In Runtime and S3 Resume: 0x2
PCH-IO Configuration
Flash Protection Range Registers (FPRR) | VarStore: PchSetup | VarOffset: 0x6DD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH-IO Configuration
SPD Write Disable | VarStore: PchSetup | VarOffset: 0x6DB | Size: 0x1
TRUE: 0x1
FALSE: 0x0
PCH-IO Configuration
LGMR | VarStore: PchSetup | VarOffset: 0x6DA | Size: 0x1
Enabled: 0x1
Disabled: 0x0
PCH-IO Configuration
Teton Glacier Mode | VarStore: PchSetup | VarOffset: 0x6E8 | Size: 0x1
Dynamic Configuration for Hybrid Storage Device Enable: 0x1
Disabled: 0x0
PCI Express Configuration
PCI Express Clock Gating | VarStore: PchSetup | VarOffset: 0xD0 | Size: 0x1
Disabled: 0x1
Enabled: 0x0
PCI Express Configuration
DMI Link ASPM Control | VarStore: PchSetup | VarOffset: 0x4F6 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Configuration
Port8xh Decode | VarStore: PchSetup | VarOffset: 0xD1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
Port8xh Decode Port# | VarStore: PchSetup | VarOffset: 0xD2 | Size: 0x1
Min: 0x0 | Max: 0x17 | Step: 0x1
PCI Express Configuration
Peer Memory Write Enable | VarStore: PchSetup | VarOffset: 0xD3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
Compliance Test Mode | VarStore: PchSetup | VarOffset: 0xD4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
PCIe-USB Glitch W/A | VarStore: PchSetup | VarOffset: 0xD5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
PCIe function swap | VarStore: PchSetup | VarOffset: 0x3C6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Configuration
Number of Coefficients to be used for equalization | VarStore: PchSetup | VarOffset: 0x6EA | Size: 0x1
Min: 0x0 | Max: 0x5 | Step: 0x1
IMR Configuration
PCIe IMR | VarStore: PchSetup | VarOffset: 0x3EA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
IMR Configuration
PCIe IMR Size | VarStore: PchSetup | VarOffset: 0x3EB | Size: 0x2
Min: 0x0 | Max: 0x400 | Step: 0x1
IMR Configuration
RP index for IMR | VarStore: PchSetup | VarOffset: 0x3ED | Size: 0x1
Min: 0x1 | Max: 0x18 | Step: 0x1
USB Configuration
XHCI Compliance Mode | VarStore: PchSetup | VarOffset: 0x3E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
xDCI Support | VarStore: PchSetup | VarOffset: 0x42 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB2 PHY Sus Well Power Gating | VarStore: PchSetup | VarOffset: 0x6E5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB Overcurrent | VarStore: PchSetup | VarOffset: 0x3F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB Overcurrent Lock | VarStore: PchSetup | VarOffset: 0x40 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB Port Disable Override | VarStore: PchSetup | VarOffset: 0x23 | Size: 0x1
Disabled: 0x0
Select Per-Pin: 0x1
USB Configuration
USB SS Physical Connector #0 | VarStore: PchSetup | VarOffset: 0x34 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB SS Physical Connector #1 | VarStore: PchSetup | VarOffset: 0x35 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB SS Physical Connector #2 | VarStore: PchSetup | VarOffset: 0x36 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB SS Physical Connector #3 | VarStore: PchSetup | VarOffset: 0x37 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB SS Physical Connector #4 | VarStore: PchSetup | VarOffset: 0x38 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB SS Physical Connector #5 | VarStore: PchSetup | VarOffset: 0x39 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB SS Physical Connector #6 | VarStore: PchSetup | VarOffset: 0x3A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB SS Physical Connector #7 | VarStore: PchSetup | VarOffset: 0x3B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB SS Physical Connector #8 | VarStore: PchSetup | VarOffset: 0x3C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB SS Physical Connector #9 | VarStore: PchSetup | VarOffset: 0x3D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #0 | VarStore: PchSetup | VarOffset: 0x24 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #1 | VarStore: PchSetup | VarOffset: 0x25 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #2 | VarStore: PchSetup | VarOffset: 0x26 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #3 | VarStore: PchSetup | VarOffset: 0x27 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #4 | VarStore: PchSetup | VarOffset: 0x28 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #5 | VarStore: PchSetup | VarOffset: 0x29 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #6 | VarStore: PchSetup | VarOffset: 0x2A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #7 | VarStore: PchSetup | VarOffset: 0x2B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #8 | VarStore: PchSetup | VarOffset: 0x2C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #9 | VarStore: PchSetup | VarOffset: 0x2D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #10 | VarStore: PchSetup | VarOffset: 0x2E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #11 | VarStore: PchSetup | VarOffset: 0x2F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #12 | VarStore: PchSetup | VarOffset: 0x30 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB HS Physical Connector #13 | VarStore: PchSetup | VarOffset: 0x31 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
USB Configuration
USB Sensor Hub | VarStore: Setup | VarOffset: 0x66 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
SATA And RST Configuration
SATA Controller(s) | VarStore: PchSetup | VarOffset: 0x43 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
SATA And RST Configuration
SATA Mode Selection | VarStore: PchSetup | VarOffset: 0x44 | Size: 0x1
AHCI: 0x0
RAID: 0x1
SATA And RST Configuration
SATA Interrupt Selection | VarStore: PchSetup | VarOffset: 0x45 | Size: 0x1
Msix: 0x0
Msi: 0x1
Legacy: 0x2
SATA And RST Configuration
PCIe Storage Dev On Port 1 | VarStore: PchSetup | VarOffset: 0xB8 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 2 | VarStore: PchSetup | VarOffset: 0xB9 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 3 | VarStore: PchSetup | VarOffset: 0xBA | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 4 | VarStore: PchSetup | VarOffset: 0xBB | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 5 | VarStore: PchSetup | VarOffset: 0xBC | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 6 | VarStore: PchSetup | VarOffset: 0xBD | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 7 | VarStore: PchSetup | VarOffset: 0xBE | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 8 | VarStore: PchSetup | VarOffset: 0xBF | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 9 | VarStore: PchSetup | VarOffset: 0xC0 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 10 | VarStore: PchSetup | VarOffset: 0xC1 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 11 | VarStore: PchSetup | VarOffset: 0xC2 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 12 | VarStore: PchSetup | VarOffset: 0xC3 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 13 | VarStore: PchSetup | VarOffset: 0xC4 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 14 | VarStore: PchSetup | VarOffset: 0xC5 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 15 | VarStore: PchSetup | VarOffset: 0xC6 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 16 | VarStore: PchSetup | VarOffset: 0xC7 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIE M.2-M1 | VarStore: PchSetup | VarOffset: 0xC8 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 18 | VarStore: PchSetup | VarOffset: 0xC9 | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 19 | VarStore: PchSetup | VarOffset: 0xCA | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 20 | VarStore: PchSetup | VarOffset: 0xCB | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 21 | VarStore: PchSetup | VarOffset: 0xCC | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 22 | VarStore: PchSetup | VarOffset: 0xCD | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 23 | VarStore: PchSetup | VarOffset: 0xCE | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
PCIe Storage Dev On Port 24 | VarStore: PchSetup | VarOffset: 0xCF | Size: 0x1
RST Controlled: 0x1
Not RST Controlled: 0x0
SATA And RST Configuration
SATA Test Mode | VarStore: PchSetup | VarOffset: 0x8F | Size: 0x1
Enabled: 0x1
Disabled: 0x0
SATA And RST Configuration
RAID Device ID | VarStore: PchSetup | VarOffset: 0x8D | Size: 0x1
iRST Mode: 0x0
Alternate: 0x1
RSTe Mode: 0x2
SATA And RST Configuration
Aggressive LPM Support | VarStore: PchSetup | VarOffset: 0x8E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Port 0 | VarStore: PchSetup | VarOffset: 0x46 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Hot Plug | VarStore: PchSetup | VarOffset: 0x4E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
External | VarStore: PchSetup | VarOffset: 0x66 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Mechanical Presence Switch | VarStore: PchSetup | VarOffset: 0x56 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Spin Up Device | VarStore: PchSetup | VarOffset: 0x5E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
SATA Device Type | VarStore: PchSetup | VarOffset: 0x6E | Size: 0x1
Hard Disk Drive: 0x0
Solid State Drive: 0x1
SATA And RST Configuration
SATA Port 0 DevSlp | VarStore: PchSetup | VarOffset: 0x90 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Configuration | VarStore: PchSetup | VarOffset: 0x98 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Value | VarStore: PchSetup | VarOffset: 0xA0 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x0
SATA And RST Configuration
DM Value | VarStore: PchSetup | VarOffset: 0xB0 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x0
SATA And RST Configuration
Port 1 | VarStore: PchSetup | VarOffset: 0x47 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Hot Plug | VarStore: PchSetup | VarOffset: 0x4F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
External | VarStore: PchSetup | VarOffset: 0x67 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Mechanical Presence Switch | VarStore: PchSetup | VarOffset: 0x57 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Spin Up Device | VarStore: PchSetup | VarOffset: 0x5F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
SATA Device Type | VarStore: PchSetup | VarOffset: 0x6F | Size: 0x1
Hard Disk Drive: 0x0
Solid State Drive: 0x1
SATA And RST Configuration
SATA Port 1 DevSlp | VarStore: PchSetup | VarOffset: 0x91 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Configuration | VarStore: PchSetup | VarOffset: 0x99 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Value | VarStore: PchSetup | VarOffset: 0xA2 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x0
SATA And RST Configuration
DM Value | VarStore: PchSetup | VarOffset: 0xB1 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x0
SATA And RST Configuration
Port 2 | VarStore: PchSetup | VarOffset: 0x48 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Hot Plug | VarStore: PchSetup | VarOffset: 0x50 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
External | VarStore: PchSetup | VarOffset: 0x68 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Mechanical Presence Switch | VarStore: PchSetup | VarOffset: 0x58 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Spin Up Device | VarStore: PchSetup | VarOffset: 0x60 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
SATA Device Type | VarStore: PchSetup | VarOffset: 0x70 | Size: 0x1
Hard Disk Drive: 0x0
Solid State Drive: 0x1
SATA And RST Configuration
SATA Port 2 DevSlp | VarStore: PchSetup | VarOffset: 0x92 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Configuration | VarStore: PchSetup | VarOffset: 0x9A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Value | VarStore: PchSetup | VarOffset: 0xA4 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x0
SATA And RST Configuration
DM Value | VarStore: PchSetup | VarOffset: 0xB2 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x0
SATA And RST Configuration
Port 3 | VarStore: PchSetup | VarOffset: 0x49 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Hot Plug | VarStore: PchSetup | VarOffset: 0x51 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
External | VarStore: PchSetup | VarOffset: 0x69 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Mechanical Presence Switch | VarStore: PchSetup | VarOffset: 0x59 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Spin Up Device | VarStore: PchSetup | VarOffset: 0x61 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
SATA Device Type | VarStore: PchSetup | VarOffset: 0x71 | Size: 0x1
Hard Disk Drive: 0x0
Solid State Drive: 0x1
SATA And RST Configuration
SATA Port 3 DevSlp | VarStore: PchSetup | VarOffset: 0x93 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Configuration | VarStore: PchSetup | VarOffset: 0x9B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Value | VarStore: PchSetup | VarOffset: 0xA6 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x0
SATA And RST Configuration
DM Value | VarStore: PchSetup | VarOffset: 0xB3 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x0
SATA And RST Configuration
Port 4 | VarStore: PchSetup | VarOffset: 0x4A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Hot Plug | VarStore: PchSetup | VarOffset: 0x52 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
External | VarStore: PchSetup | VarOffset: 0x6A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Mechanical Presence Switch | VarStore: PchSetup | VarOffset: 0x5A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Spin Up Device | VarStore: PchSetup | VarOffset: 0x62 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
SATA Device Type | VarStore: PchSetup | VarOffset: 0x72 | Size: 0x1
Hard Disk Drive: 0x0
Solid State Drive: 0x1
SATA And RST Configuration
SATA Port 4 DevSlp | VarStore: PchSetup | VarOffset: 0x94 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Configuration | VarStore: PchSetup | VarOffset: 0x9C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Value | VarStore: PchSetup | VarOffset: 0xA8 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x0
SATA And RST Configuration
DM Value | VarStore: PchSetup | VarOffset: 0xB4 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x0
SATA And RST Configuration
Port 5 | VarStore: PchSetup | VarOffset: 0x4B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Hot Plug | VarStore: PchSetup | VarOffset: 0x53 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
External | VarStore: PchSetup | VarOffset: 0x6B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Mechanical Presence Switch | VarStore: PchSetup | VarOffset: 0x5B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Spin Up Device | VarStore: PchSetup | VarOffset: 0x63 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
SATA Device Type | VarStore: PchSetup | VarOffset: 0x73 | Size: 0x1
Hard Disk Drive: 0x0
Solid State Drive: 0x1
SATA And RST Configuration
SATA Port 5 DevSlp | VarStore: PchSetup | VarOffset: 0x95 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Configuration | VarStore: PchSetup | VarOffset: 0x9D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Value | VarStore: PchSetup | VarOffset: 0xAA | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x0
SATA And RST Configuration
DM Value | VarStore: PchSetup | VarOffset: 0xB5 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x0
SATA And RST Configuration
Port 6 | VarStore: PchSetup | VarOffset: 0x4C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Hot Plug | VarStore: PchSetup | VarOffset: 0x54 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
External | VarStore: PchSetup | VarOffset: 0x6C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Mechanical Presence Switch | VarStore: PchSetup | VarOffset: 0x5C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Spin Up Device | VarStore: PchSetup | VarOffset: 0x64 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
SATA Device Type | VarStore: PchSetup | VarOffset: 0x74 | Size: 0x1
Hard Disk Drive: 0x0
Solid State Drive: 0x1
SATA And RST Configuration
SATA Port 6 DevSlp | VarStore: PchSetup | VarOffset: 0x96 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Configuration | VarStore: PchSetup | VarOffset: 0x9E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Value | VarStore: PchSetup | VarOffset: 0xAC | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x0
SATA And RST Configuration
DM Value | VarStore: PchSetup | VarOffset: 0xB6 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x0
SATA And RST Configuration
Port 7 | VarStore: PchSetup | VarOffset: 0x4D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Hot Plug | VarStore: PchSetup | VarOffset: 0x55 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
External | VarStore: PchSetup | VarOffset: 0x6D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Mechanical Presence Switch | VarStore: PchSetup | VarOffset: 0x5D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
Spin Up Device | VarStore: PchSetup | VarOffset: 0x65 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
SATA Device Type | VarStore: PchSetup | VarOffset: 0x75 | Size: 0x1
Hard Disk Drive: 0x0
Solid State Drive: 0x1
SATA And RST Configuration
SATA Port 7 DevSlp | VarStore: PchSetup | VarOffset: 0x97 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Configuration | VarStore: PchSetup | VarOffset: 0x9F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SATA And RST Configuration
DITO Value | VarStore: PchSetup | VarOffset: 0xAE | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x0
SATA And RST Configuration
DM Value | VarStore: PchSetup | VarOffset: 0xB7 | Size: 0x1
Min: 0x0 | Max: 0xF | Step: 0x0
Software Feature Mask Configuration
HDD Unlock | VarStore: PchSetup | VarOffset: 0x84 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Software Feature Mask Configuration
LED Locate | VarStore: PchSetup | VarOffset: 0x85 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Software Feature Mask Configuration
Use RST Legacy OROM | VarStore: PchSetup | VarOffset: 0x8A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Software Feature Mask Configuration
RAID0 | VarStore: PchSetup | VarOffset: 0x7E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Software Feature Mask Configuration
RAID1 | VarStore: PchSetup | VarOffset: 0x7F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Software Feature Mask Configuration
RAID10 | VarStore: PchSetup | VarOffset: 0x80 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Software Feature Mask Configuration
RAID5 | VarStore: PchSetup | VarOffset: 0x81 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Software Feature Mask Configuration
Intel Rapid Recovery Technology | VarStore: PchSetup | VarOffset: 0x82 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Software Feature Mask Configuration
OROM UI and BANNER | VarStore: PchSetup | VarOffset: 0x83 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Software Feature Mask Configuration
IRRT Only on eSATA | VarStore: PchSetup | VarOffset: 0x86 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Software Feature Mask Configuration
Smart Response Technology | VarStore: PchSetup | VarOffset: 0x87 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Software Feature Mask Configuration
OROM UI Normal Delay | VarStore: PchSetup | VarOffset: 0x88 | Size: 0x1
2 secs: 0x0
4 secs: 0x1
6 secs: 0x2
8 secs: 0x3
Software Feature Mask Configuration
RST Force Form | VarStore: PchSetup | VarOffset: 0x89 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Software Feature Mask Configuration
System Acceleration with Intel(R) Optane(TM) Memory | VarStore: PchSetup | VarOffset: 0x8B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Software Feature Mask Configuration
CPU Attached Storage | VarStore: PchSetup | VarOffset: 0x8C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Gen3 Eq Lanes
PCIE1 Cm | VarStore: PchSetup | VarOffset: 0x336 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE1 Cp | VarStore: PchSetup | VarOffset: 0x34E | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE2 Cm | VarStore: PchSetup | VarOffset: 0x337 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE2 Cp | VarStore: PchSetup | VarOffset: 0x34F | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE3 Cm | VarStore: PchSetup | VarOffset: 0x338 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE3 Cp | VarStore: PchSetup | VarOffset: 0x350 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE4 Cm | VarStore: PchSetup | VarOffset: 0x339 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE4 Cp | VarStore: PchSetup | VarOffset: 0x351 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE5 Cm | VarStore: PchSetup | VarOffset: 0x33A | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE5 Cp | VarStore: PchSetup | VarOffset: 0x352 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE6 Cm | VarStore: PchSetup | VarOffset: 0x33B | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE6 Cp | VarStore: PchSetup | VarOffset: 0x353 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE7 Cm | VarStore: PchSetup | VarOffset: 0x33C | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE7 Cp | VarStore: PchSetup | VarOffset: 0x354 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE8 Cm | VarStore: PchSetup | VarOffset: 0x33D | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE8 Cp | VarStore: PchSetup | VarOffset: 0x355 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE9 Cm | VarStore: PchSetup | VarOffset: 0x33E | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE9 Cp | VarStore: PchSetup | VarOffset: 0x356 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE10 Cm | VarStore: PchSetup | VarOffset: 0x33F | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE10 Cp | VarStore: PchSetup | VarOffset: 0x357 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE11 Cm | VarStore: PchSetup | VarOffset: 0x340 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE11 Cp | VarStore: PchSetup | VarOffset: 0x358 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE12 Cm | VarStore: PchSetup | VarOffset: 0x341 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE12 Cp | VarStore: PchSetup | VarOffset: 0x359 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE13 Cm | VarStore: PchSetup | VarOffset: 0x342 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE13 Cp | VarStore: PchSetup | VarOffset: 0x35A | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE14 Cm | VarStore: PchSetup | VarOffset: 0x343 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE14 Cp | VarStore: PchSetup | VarOffset: 0x35B | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE15 Cm | VarStore: PchSetup | VarOffset: 0x344 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE15 Cp | VarStore: PchSetup | VarOffset: 0x35C | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE16 Cm | VarStore: PchSetup | VarOffset: 0x345 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE16 Cp | VarStore: PchSetup | VarOffset: 0x35D | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE17 Cm | VarStore: PchSetup | VarOffset: 0x346 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE17 Cp | VarStore: PchSetup | VarOffset: 0x35E | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE18 Cm | VarStore: PchSetup | VarOffset: 0x347 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE18 Cp | VarStore: PchSetup | VarOffset: 0x35F | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE19 Cm | VarStore: PchSetup | VarOffset: 0x348 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE19 Cp | VarStore: PchSetup | VarOffset: 0x360 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE20 Cm | VarStore: PchSetup | VarOffset: 0x349 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE20 Cp | VarStore: PchSetup | VarOffset: 0x361 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE21 Cm | VarStore: PchSetup | VarOffset: 0x34A | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE21 Cp | VarStore: PchSetup | VarOffset: 0x362 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE22 Cm | VarStore: PchSetup | VarOffset: 0x34B | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE22 Cp | VarStore: PchSetup | VarOffset: 0x363 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE23 Cm | VarStore: PchSetup | VarOffset: 0x34C | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE23 Cp | VarStore: PchSetup | VarOffset: 0x364 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE24 Cm | VarStore: PchSetup | VarOffset: 0x34D | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
PCIE24 Cp | VarStore: PchSetup | VarOffset: 0x365 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
Override SW EQ settings | VarStore: PchSetup | VarOffset: 0x3DF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Gen3 Eq Lanes
Coeff0 Cm | VarStore: PchSetup | VarOffset: 0x3E0 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
Coeff0 Cp | VarStore: PchSetup | VarOffset: 0x3E5 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
Coeff1 Cm | VarStore: PchSetup | VarOffset: 0x3E1 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
Coeff1 Cp | VarStore: PchSetup | VarOffset: 0x3E6 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
Coeff2 Cm | VarStore: PchSetup | VarOffset: 0x3E2 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
Coeff2 Cp | VarStore: PchSetup | VarOffset: 0x3E7 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
Coeff3 Cm | VarStore: PchSetup | VarOffset: 0x3E3 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
Coeff3 Cp | VarStore: PchSetup | VarOffset: 0x3E8 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
Coeff4 Cm | VarStore: PchSetup | VarOffset: 0x3E4 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCI Express Gen3 Eq Lanes
Coeff4 Cp | VarStore: PchSetup | VarOffset: 0x3E9 | Size: 0x1
Min: 0x0 | Max: 0x3F | Step: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
PCI Express Root Port 1 | VarStore: PchSetup | VarOffset: 0xF6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
Disable Gen2 Pll Shutdown and L1 Controller Power gating | VarStore: PchSetup | VarOffset: 0x3C7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
Connection Type | VarStore: PchSetup | VarOffset: 0x37E | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
SLOT4 ASPM | VarStore: PchSetup | VarOffset: 0x10E | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
SLOT4 L1 Substates | VarStore: PchSetup | VarOffset: 0x276 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
Gen3 Eq Phase3 Method | VarStore: PchSetup | VarOffset: 0x2EE | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
UPTP | VarStore: PchSetup | VarOffset: 0x306 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
DPTP | VarStore: PchSetup | VarOffset: 0x31E | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
ACS | VarStore: PchSetup | VarOffset: 0x28E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
PTM | VarStore: PchSetup | VarOffset: 0x2A6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
DPC | VarStore: PchSetup | VarOffset: 0x2BE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
EDPC | VarStore: PchSetup | VarOffset: 0x2D6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
URR | VarStore: PchSetup | VarOffset: 0x126 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
FER | VarStore: PchSetup | VarOffset: 0x13E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
NFER | VarStore: PchSetup | VarOffset: 0x156 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
CER | VarStore: PchSetup | VarOffset: 0x16E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
CTO | VarStore: PchSetup | VarOffset: 0x186 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
SEFE | VarStore: PchSetup | VarOffset: 0x1B6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
SENFE | VarStore: PchSetup | VarOffset: 0x1CE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
SECE | VarStore: PchSetup | VarOffset: 0x1E6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
PME SCI | VarStore: PchSetup | VarOffset: 0x1FE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
Hot Plug | VarStore: PchSetup | VarOffset: 0x216 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x22E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
PCIe Speed | VarStore: PchSetup | VarOffset: 0x246 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x25E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
Detect Timeout | VarStore: PchSetup | VarOffset: 0x396 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x4F7 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
Reserved Memory | VarStore: PchSetup | VarOffset: 0x50F | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
Reserved I/O | VarStore: PchSetup | VarOffset: 0x53F | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
LTR | VarStore: PchSetup | VarOffset: 0x3EE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x41E | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x47E | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x436 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x44E | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4AE | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x466 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
Force LTR Override | VarStore: PchSetup | VarOffset: 0x4DE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT4 PCI-E 3.0 X4 (IN X8)
LTR Lock | VarStore: PchSetup | VarOffset: 0x406 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
PCI Express Root Port 2 | VarStore: PchSetup | VarOffset: 0xF7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
Disable Gen2 Pll Shutdown and L1 Controller Power gating | VarStore: PchSetup | VarOffset: 0x3C8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
Connection Type | VarStore: PchSetup | VarOffset: 0x37F | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 2
ASPM 1 | VarStore: PchSetup | VarOffset: 0x10F | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 2
L1 SubStates | VarStore: PchSetup | VarOffset: 0x277 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 2
Gen3 Eq Phase3 Method | VarStore: PchSetup | VarOffset: 0x2EF | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 2
UPTP | VarStore: PchSetup | VarOffset: 0x307 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 2
DPTP | VarStore: PchSetup | VarOffset: 0x31F | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 2
ACS | VarStore: PchSetup | VarOffset: 0x28F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
PTM | VarStore: PchSetup | VarOffset: 0x2A7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
DPC | VarStore: PchSetup | VarOffset: 0x2BF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
EDPC | VarStore: PchSetup | VarOffset: 0x2D7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
URR | VarStore: PchSetup | VarOffset: 0x127 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
FER | VarStore: PchSetup | VarOffset: 0x13F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
NFER | VarStore: PchSetup | VarOffset: 0x157 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
CER | VarStore: PchSetup | VarOffset: 0x16F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
CTO | VarStore: PchSetup | VarOffset: 0x187 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
SEFE | VarStore: PchSetup | VarOffset: 0x1B7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
SENFE | VarStore: PchSetup | VarOffset: 0x1CF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
SECE | VarStore: PchSetup | VarOffset: 0x1E7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
PME SCI | VarStore: PchSetup | VarOffset: 0x1FF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
Hot Plug | VarStore: PchSetup | VarOffset: 0x217 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x22F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
PCIe Speed | VarStore: PchSetup | VarOffset: 0x247 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 2
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x25F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
Detect Timeout | VarStore: PchSetup | VarOffset: 0x398 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 2
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x4F8 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 2
Reserved Memory | VarStore: PchSetup | VarOffset: 0x511 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 2
Reserved I/O | VarStore: PchSetup | VarOffset: 0x540 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 2
LTR | VarStore: PchSetup | VarOffset: 0x3EF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x41F | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 2
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x480 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 2
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x437 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 2
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x44F | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 2
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4B0 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 2
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x467 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 2
Force LTR Override | VarStore: PchSetup | VarOffset: 0x4DF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 2
LTR Lock | VarStore: PchSetup | VarOffset: 0x407 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
PCI Express Root Port 3 | VarStore: PchSetup | VarOffset: 0xF8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
Disable Gen2 Pll Shutdown and L1 Controller Power gating | VarStore: PchSetup | VarOffset: 0x3C9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
Connection Type | VarStore: PchSetup | VarOffset: 0x380 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 3
ASPM 2 | VarStore: PchSetup | VarOffset: 0x110 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 3
L1 SubStates | VarStore: PchSetup | VarOffset: 0x278 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 3
Gen3 Eq Phase3 Method | VarStore: PchSetup | VarOffset: 0x2F0 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 3
UPTP | VarStore: PchSetup | VarOffset: 0x308 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 3
DPTP | VarStore: PchSetup | VarOffset: 0x320 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 3
ACS | VarStore: PchSetup | VarOffset: 0x290 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
PTM | VarStore: PchSetup | VarOffset: 0x2A8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
DPC | VarStore: PchSetup | VarOffset: 0x2C0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
EDPC | VarStore: PchSetup | VarOffset: 0x2D8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
URR | VarStore: PchSetup | VarOffset: 0x128 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
FER | VarStore: PchSetup | VarOffset: 0x140 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
NFER | VarStore: PchSetup | VarOffset: 0x158 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
CER | VarStore: PchSetup | VarOffset: 0x170 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
CTO | VarStore: PchSetup | VarOffset: 0x188 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
SEFE | VarStore: PchSetup | VarOffset: 0x1B8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
SENFE | VarStore: PchSetup | VarOffset: 0x1D0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
SECE | VarStore: PchSetup | VarOffset: 0x1E8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
PME SCI | VarStore: PchSetup | VarOffset: 0x200 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
Hot Plug | VarStore: PchSetup | VarOffset: 0x218 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x230 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
PCIe Speed | VarStore: PchSetup | VarOffset: 0x248 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 3
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x260 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
Detect Timeout | VarStore: PchSetup | VarOffset: 0x39A | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 3
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x4F9 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 3
Reserved Memory | VarStore: PchSetup | VarOffset: 0x513 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 3
Reserved I/O | VarStore: PchSetup | VarOffset: 0x541 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 3
LTR | VarStore: PchSetup | VarOffset: 0x3F0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x420 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 3
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x482 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 3
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x438 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 3
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x450 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 3
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4B2 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 3
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x468 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 3
Force LTR Override | VarStore: PchSetup | VarOffset: 0x4E0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 3
LTR Lock | VarStore: PchSetup | VarOffset: 0x408 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
PCI Express Root Port 4 | VarStore: PchSetup | VarOffset: 0xF9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
Disable Gen2 Pll Shutdown and L1 Controller Power gating | VarStore: PchSetup | VarOffset: 0x3CA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
Connection Type | VarStore: PchSetup | VarOffset: 0x381 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 4
ASPM 3 | VarStore: PchSetup | VarOffset: 0x111 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 4
L1 SubStates | VarStore: PchSetup | VarOffset: 0x279 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 4
Gen3 Eq Phase3 Method | VarStore: PchSetup | VarOffset: 0x2F1 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 4
UPTP | VarStore: PchSetup | VarOffset: 0x309 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 4
DPTP | VarStore: PchSetup | VarOffset: 0x321 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 4
ACS | VarStore: PchSetup | VarOffset: 0x291 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
PTM | VarStore: PchSetup | VarOffset: 0x2A9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
DPC | VarStore: PchSetup | VarOffset: 0x2C1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
EDPC | VarStore: PchSetup | VarOffset: 0x2D9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
URR | VarStore: PchSetup | VarOffset: 0x129 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
FER | VarStore: PchSetup | VarOffset: 0x141 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
NFER | VarStore: PchSetup | VarOffset: 0x159 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
CER | VarStore: PchSetup | VarOffset: 0x171 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
CTO | VarStore: PchSetup | VarOffset: 0x189 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
SEFE | VarStore: PchSetup | VarOffset: 0x1B9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
SENFE | VarStore: PchSetup | VarOffset: 0x1D1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
SECE | VarStore: PchSetup | VarOffset: 0x1E9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
PME SCI | VarStore: PchSetup | VarOffset: 0x201 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
Hot Plug | VarStore: PchSetup | VarOffset: 0x219 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x231 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
PCIe Speed | VarStore: PchSetup | VarOffset: 0x249 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 4
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x261 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
Detect Timeout | VarStore: PchSetup | VarOffset: 0x39C | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 4
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x4FA | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 4
Reserved Memory | VarStore: PchSetup | VarOffset: 0x515 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 4
Reserved I/O | VarStore: PchSetup | VarOffset: 0x542 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 4
LTR | VarStore: PchSetup | VarOffset: 0x3F1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x421 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 4
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x484 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 4
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x439 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 4
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x451 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 4
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4B4 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 4
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x469 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 4
Force LTR Override | VarStore: PchSetup | VarOffset: 0x4E1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 4
LTR Lock | VarStore: PchSetup | VarOffset: 0x409 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
PCI Express Root Port 5 | VarStore: PchSetup | VarOffset: 0xFA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
Disable Gen2 Pll Shutdown and L1 Controller Power gating | VarStore: PchSetup | VarOffset: 0x3CB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
Connection Type | VarStore: PchSetup | VarOffset: 0x382 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 5
ASPM 4 | VarStore: PchSetup | VarOffset: 0x112 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 5
L1 SubStates | VarStore: PchSetup | VarOffset: 0x27A | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 5
Gen3 Eq Phase3 Method | VarStore: PchSetup | VarOffset: 0x2F2 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 5
UPTP | VarStore: PchSetup | VarOffset: 0x30A | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 5
DPTP | VarStore: PchSetup | VarOffset: 0x322 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 5
ACS | VarStore: PchSetup | VarOffset: 0x292 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
PTM | VarStore: PchSetup | VarOffset: 0x2AA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
DPC | VarStore: PchSetup | VarOffset: 0x2C2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
EDPC | VarStore: PchSetup | VarOffset: 0x2DA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
URR | VarStore: PchSetup | VarOffset: 0x12A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
FER | VarStore: PchSetup | VarOffset: 0x142 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
NFER | VarStore: PchSetup | VarOffset: 0x15A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
CER | VarStore: PchSetup | VarOffset: 0x172 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
CTO | VarStore: PchSetup | VarOffset: 0x18A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
SEFE | VarStore: PchSetup | VarOffset: 0x1BA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
SENFE | VarStore: PchSetup | VarOffset: 0x1D2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
SECE | VarStore: PchSetup | VarOffset: 0x1EA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
PME SCI | VarStore: PchSetup | VarOffset: 0x202 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
Hot Plug | VarStore: PchSetup | VarOffset: 0x21A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x232 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
PCIe Speed | VarStore: PchSetup | VarOffset: 0x24A | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 5
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x262 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
Detect Timeout | VarStore: PchSetup | VarOffset: 0x39E | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 5
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x4FB | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 5
Reserved Memory | VarStore: PchSetup | VarOffset: 0x517 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 5
Reserved I/O | VarStore: PchSetup | VarOffset: 0x543 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 5
LTR | VarStore: PchSetup | VarOffset: 0x3F2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x422 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 5
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x486 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 5
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x43A | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 5
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x452 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 5
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4B6 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 5
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x46A | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 5
Force LTR Override | VarStore: PchSetup | VarOffset: 0x4E2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 5
LTR Lock | VarStore: PchSetup | VarOffset: 0x40A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
PCI Express Root Port 6 | VarStore: PchSetup | VarOffset: 0xFB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
Disable Gen2 Pll Shutdown and L1 Controller Power gating | VarStore: PchSetup | VarOffset: 0x3CC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
Connection Type | VarStore: PchSetup | VarOffset: 0x383 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 6
ASPM 5 | VarStore: PchSetup | VarOffset: 0x113 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 6
L1 SubStates | VarStore: PchSetup | VarOffset: 0x27B | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 6
Gen3 Eq Phase3 Method | VarStore: PchSetup | VarOffset: 0x2F3 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 6
UPTP | VarStore: PchSetup | VarOffset: 0x30B | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 6
DPTP | VarStore: PchSetup | VarOffset: 0x323 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 6
ACS | VarStore: PchSetup | VarOffset: 0x293 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
PTM | VarStore: PchSetup | VarOffset: 0x2AB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
DPC | VarStore: PchSetup | VarOffset: 0x2C3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
EDPC | VarStore: PchSetup | VarOffset: 0x2DB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
URR | VarStore: PchSetup | VarOffset: 0x12B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
FER | VarStore: PchSetup | VarOffset: 0x143 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
NFER | VarStore: PchSetup | VarOffset: 0x15B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
CER | VarStore: PchSetup | VarOffset: 0x173 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
CTO | VarStore: PchSetup | VarOffset: 0x18B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
SEFE | VarStore: PchSetup | VarOffset: 0x1BB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
SENFE | VarStore: PchSetup | VarOffset: 0x1D3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
SECE | VarStore: PchSetup | VarOffset: 0x1EB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
PME SCI | VarStore: PchSetup | VarOffset: 0x203 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
Hot Plug | VarStore: PchSetup | VarOffset: 0x21B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x233 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
PCIe Speed | VarStore: PchSetup | VarOffset: 0x24B | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 6
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x263 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
Detect Timeout | VarStore: PchSetup | VarOffset: 0x3A0 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 6
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x4FC | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 6
Reserved Memory | VarStore: PchSetup | VarOffset: 0x519 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 6
Reserved I/O | VarStore: PchSetup | VarOffset: 0x544 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 6
LTR | VarStore: PchSetup | VarOffset: 0x3F3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x423 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 6
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x488 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 6
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x43B | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 6
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x453 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 6
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4B8 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 6
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x46B | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 6
Force LTR Override | VarStore: PchSetup | VarOffset: 0x4E3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 6
LTR Lock | VarStore: PchSetup | VarOffset: 0x40B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
PCI Express Root Port 7 | VarStore: PchSetup | VarOffset: 0xFC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
Disable Gen2 Pll Shutdown and L1 Controller Power gating | VarStore: PchSetup | VarOffset: 0x3CD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
Connection Type | VarStore: PchSetup | VarOffset: 0x384 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 7
ASPM 6 | VarStore: PchSetup | VarOffset: 0x114 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 7
L1 SubStates | VarStore: PchSetup | VarOffset: 0x27C | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 7
Gen3 Eq Phase3 Method | VarStore: PchSetup | VarOffset: 0x2F4 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 7
UPTP | VarStore: PchSetup | VarOffset: 0x30C | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 7
DPTP | VarStore: PchSetup | VarOffset: 0x324 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 7
ACS | VarStore: PchSetup | VarOffset: 0x294 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
PTM | VarStore: PchSetup | VarOffset: 0x2AC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
DPC | VarStore: PchSetup | VarOffset: 0x2C4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
EDPC | VarStore: PchSetup | VarOffset: 0x2DC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
URR | VarStore: PchSetup | VarOffset: 0x12C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
FER | VarStore: PchSetup | VarOffset: 0x144 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
NFER | VarStore: PchSetup | VarOffset: 0x15C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
CER | VarStore: PchSetup | VarOffset: 0x174 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
CTO | VarStore: PchSetup | VarOffset: 0x18C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
SEFE | VarStore: PchSetup | VarOffset: 0x1BC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
SENFE | VarStore: PchSetup | VarOffset: 0x1D4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
SECE | VarStore: PchSetup | VarOffset: 0x1EC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
PME SCI | VarStore: PchSetup | VarOffset: 0x204 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
Hot Plug | VarStore: PchSetup | VarOffset: 0x21C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x234 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
PCIe Speed | VarStore: PchSetup | VarOffset: 0x24C | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 7
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x264 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
Detect Timeout | VarStore: PchSetup | VarOffset: 0x3A2 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 7
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x4FD | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 7
Reserved Memory | VarStore: PchSetup | VarOffset: 0x51B | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 7
Reserved I/O | VarStore: PchSetup | VarOffset: 0x545 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 7
LTR | VarStore: PchSetup | VarOffset: 0x3F4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x424 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 7
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x48A | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 7
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x43C | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 7
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x454 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 7
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4BA | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 7
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x46C | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 7
Force LTR Override | VarStore: PchSetup | VarOffset: 0x4E4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 7
LTR Lock | VarStore: PchSetup | VarOffset: 0x40C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-E1
PCI Express Root Port 8 | VarStore: PchSetup | VarOffset: 0xFD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-E1
Disable Gen2 Pll Shutdown and L1 Controller Power gating | VarStore: PchSetup | VarOffset: 0x3CE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-E1
Connection Type | VarStore: PchSetup | VarOffset: 0x385 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI-E M.2-E1
M.2-E1 ASPM | VarStore: PchSetup | VarOffset: 0x115 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI-E M.2-E1
M.2-E1 L1 Substates | VarStore: PchSetup | VarOffset: 0x27D | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI-E M.2-E1
Gen3 Eq Phase3 Method | VarStore: PchSetup | VarOffset: 0x2F5 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI-E M.2-E1
UPTP | VarStore: PchSetup | VarOffset: 0x30D | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI-E M.2-E1
DPTP | VarStore: PchSetup | VarOffset: 0x325 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI-E M.2-E1
ACS | VarStore: PchSetup | VarOffset: 0x295 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-E1
PTM | VarStore: PchSetup | VarOffset: 0x2AD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-E1
DPC | VarStore: PchSetup | VarOffset: 0x2C5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-E1
EDPC | VarStore: PchSetup | VarOffset: 0x2DD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-E1
URR | VarStore: PchSetup | VarOffset: 0x12D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-E1
FER | VarStore: PchSetup | VarOffset: 0x145 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-E1
NFER | VarStore: PchSetup | VarOffset: 0x15D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-E1
CER | VarStore: PchSetup | VarOffset: 0x175 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-E1
CTO | VarStore: PchSetup | VarOffset: 0x18D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-E1
SEFE | VarStore: PchSetup | VarOffset: 0x1BD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-E1
SENFE | VarStore: PchSetup | VarOffset: 0x1D5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-E1
SECE | VarStore: PchSetup | VarOffset: 0x1ED | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-E1
PME SCI | VarStore: PchSetup | VarOffset: 0x205 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-E1
Hot Plug | VarStore: PchSetup | VarOffset: 0x21D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-E1
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x235 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-E1
PCIe Speed | VarStore: PchSetup | VarOffset: 0x24D | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI-E M.2-E1
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x265 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-E1
Detect Timeout | VarStore: PchSetup | VarOffset: 0x3A4 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI-E M.2-E1
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x4FE | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI-E M.2-E1
Reserved Memory | VarStore: PchSetup | VarOffset: 0x51D | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI-E M.2-E1
Reserved I/O | VarStore: PchSetup | VarOffset: 0x546 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI-E M.2-E1
LTR | VarStore: PchSetup | VarOffset: 0x3F5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-E1
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x425 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI-E M.2-E1
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x48C | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI-E M.2-E1
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x43D | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI-E M.2-E1
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x455 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI-E M.2-E1
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4BC | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI-E M.2-E1
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x46D | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI-E M.2-E1
Force LTR Override | VarStore: PchSetup | VarOffset: 0x4E5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-E1
LTR Lock | VarStore: PchSetup | VarOffset: 0x40D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
PCI Express Root Port 9 | VarStore: PchSetup | VarOffset: 0xFE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
Disable Gen2 Pll Shutdown and L1 Controller Power gating | VarStore: PchSetup | VarOffset: 0x3CF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
Connection Type | VarStore: PchSetup | VarOffset: 0x386 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 9
ASPM 8 | VarStore: PchSetup | VarOffset: 0x116 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 9
L1 SubStates | VarStore: PchSetup | VarOffset: 0x27E | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 9
Gen3 Eq Phase3 Method | VarStore: PchSetup | VarOffset: 0x2F6 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 9
UPTP | VarStore: PchSetup | VarOffset: 0x30E | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 9
DPTP | VarStore: PchSetup | VarOffset: 0x326 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 9
ACS | VarStore: PchSetup | VarOffset: 0x296 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
PTM | VarStore: PchSetup | VarOffset: 0x2AE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
DPC | VarStore: PchSetup | VarOffset: 0x2C6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
EDPC | VarStore: PchSetup | VarOffset: 0x2DE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
URR | VarStore: PchSetup | VarOffset: 0x12E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
FER | VarStore: PchSetup | VarOffset: 0x146 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
NFER | VarStore: PchSetup | VarOffset: 0x15E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
CER | VarStore: PchSetup | VarOffset: 0x176 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
CTO | VarStore: PchSetup | VarOffset: 0x18E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
SEFE | VarStore: PchSetup | VarOffset: 0x1BE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
SENFE | VarStore: PchSetup | VarOffset: 0x1D6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
SECE | VarStore: PchSetup | VarOffset: 0x1EE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
PME SCI | VarStore: PchSetup | VarOffset: 0x206 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
Hot Plug | VarStore: PchSetup | VarOffset: 0x21E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x236 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
PCIe Speed | VarStore: PchSetup | VarOffset: 0x24E | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 9
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x266 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
Detect Timeout | VarStore: PchSetup | VarOffset: 0x3A6 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 9
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x4FF | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 9
Reserved Memory | VarStore: PchSetup | VarOffset: 0x51F | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 9
Reserved I/O | VarStore: PchSetup | VarOffset: 0x547 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 9
LTR | VarStore: PchSetup | VarOffset: 0x3F6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x426 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 9
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x48E | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 9
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x43E | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 9
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x456 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 9
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4BE | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 9
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x46E | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 9
Force LTR Override | VarStore: PchSetup | VarOffset: 0x4E6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 9
LTR Lock | VarStore: PchSetup | VarOffset: 0x40E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
PCI Express Root Port 10 | VarStore: PchSetup | VarOffset: 0xFF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
Disable Gen2 Pll Shutdown and L1 Controller Power gating | VarStore: PchSetup | VarOffset: 0x3D0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
Connection Type | VarStore: PchSetup | VarOffset: 0x387 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 10
ASPM 9 | VarStore: PchSetup | VarOffset: 0x117 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 10
L1 SubStates | VarStore: PchSetup | VarOffset: 0x27F | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 10
Gen3 Eq Phase3 Method | VarStore: PchSetup | VarOffset: 0x2F7 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 10
UPTP | VarStore: PchSetup | VarOffset: 0x30F | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 10
DPTP | VarStore: PchSetup | VarOffset: 0x327 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 10
ACS | VarStore: PchSetup | VarOffset: 0x297 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
PTM | VarStore: PchSetup | VarOffset: 0x2AF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
DPC | VarStore: PchSetup | VarOffset: 0x2C7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
EDPC | VarStore: PchSetup | VarOffset: 0x2DF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
URR | VarStore: PchSetup | VarOffset: 0x12F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
FER | VarStore: PchSetup | VarOffset: 0x147 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
NFER | VarStore: PchSetup | VarOffset: 0x15F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
CER | VarStore: PchSetup | VarOffset: 0x177 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
CTO | VarStore: PchSetup | VarOffset: 0x18F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
SEFE | VarStore: PchSetup | VarOffset: 0x1BF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
SENFE | VarStore: PchSetup | VarOffset: 0x1D7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
SECE | VarStore: PchSetup | VarOffset: 0x1EF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
PME SCI | VarStore: PchSetup | VarOffset: 0x207 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
Hot Plug | VarStore: PchSetup | VarOffset: 0x21F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x237 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
PCIe Speed | VarStore: PchSetup | VarOffset: 0x24F | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 10
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x267 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
Detect Timeout | VarStore: PchSetup | VarOffset: 0x3A8 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 10
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x500 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 10
Reserved Memory | VarStore: PchSetup | VarOffset: 0x521 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 10
Reserved I/O | VarStore: PchSetup | VarOffset: 0x548 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 10
LTR | VarStore: PchSetup | VarOffset: 0x3F7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x427 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 10
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x490 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 10
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x43F | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 10
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x457 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 10
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4C0 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 10
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x46F | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 10
Force LTR Override | VarStore: PchSetup | VarOffset: 0x4E7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 10
LTR Lock | VarStore: PchSetup | VarOffset: 0x40F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
PCI Express Root Port 11 | VarStore: PchSetup | VarOffset: 0x100 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
Disable Gen2 Pll Shutdown and L1 Controller Power gating | VarStore: PchSetup | VarOffset: 0x3D1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
Connection Type | VarStore: PchSetup | VarOffset: 0x388 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 11
ASPM 10 | VarStore: PchSetup | VarOffset: 0x118 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 11
L1 SubStates | VarStore: PchSetup | VarOffset: 0x280 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 11
Gen3 Eq Phase3 Method | VarStore: PchSetup | VarOffset: 0x2F8 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 11
UPTP | VarStore: PchSetup | VarOffset: 0x310 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 11
DPTP | VarStore: PchSetup | VarOffset: 0x328 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 11
ACS | VarStore: PchSetup | VarOffset: 0x298 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
PTM | VarStore: PchSetup | VarOffset: 0x2B0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
DPC | VarStore: PchSetup | VarOffset: 0x2C8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
EDPC | VarStore: PchSetup | VarOffset: 0x2E0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
URR | VarStore: PchSetup | VarOffset: 0x130 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
FER | VarStore: PchSetup | VarOffset: 0x148 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
NFER | VarStore: PchSetup | VarOffset: 0x160 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
CER | VarStore: PchSetup | VarOffset: 0x178 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
CTO | VarStore: PchSetup | VarOffset: 0x190 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
SEFE | VarStore: PchSetup | VarOffset: 0x1C0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
SENFE | VarStore: PchSetup | VarOffset: 0x1D8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
SECE | VarStore: PchSetup | VarOffset: 0x1F0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
PME SCI | VarStore: PchSetup | VarOffset: 0x208 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
Hot Plug | VarStore: PchSetup | VarOffset: 0x220 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x238 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
PCIe Speed | VarStore: PchSetup | VarOffset: 0x250 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 11
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x268 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
Detect Timeout | VarStore: PchSetup | VarOffset: 0x3AA | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 11
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x501 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 11
Reserved Memory | VarStore: PchSetup | VarOffset: 0x523 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 11
Reserved I/O | VarStore: PchSetup | VarOffset: 0x549 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 11
LTR | VarStore: PchSetup | VarOffset: 0x3F8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x428 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 11
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x492 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 11
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x440 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 11
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x458 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 11
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4C2 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 11
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x470 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 11
Force LTR Override | VarStore: PchSetup | VarOffset: 0x4E8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 11
LTR Lock | VarStore: PchSetup | VarOffset: 0x410 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
PCI Express Root Port 12 | VarStore: PchSetup | VarOffset: 0x101 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
Disable Gen2 Pll Shutdown and L1 Controller Power gating | VarStore: PchSetup | VarOffset: 0x3D2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
Connection Type | VarStore: PchSetup | VarOffset: 0x389 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 12
ASPM 11 | VarStore: PchSetup | VarOffset: 0x119 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 12
L1 SubStates | VarStore: PchSetup | VarOffset: 0x281 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 12
Gen3 Eq Phase3 Method | VarStore: PchSetup | VarOffset: 0x2F9 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 12
UPTP | VarStore: PchSetup | VarOffset: 0x311 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 12
DPTP | VarStore: PchSetup | VarOffset: 0x329 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 12
ACS | VarStore: PchSetup | VarOffset: 0x299 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
PTM | VarStore: PchSetup | VarOffset: 0x2B1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
DPC | VarStore: PchSetup | VarOffset: 0x2C9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
EDPC | VarStore: PchSetup | VarOffset: 0x2E1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
URR | VarStore: PchSetup | VarOffset: 0x131 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
FER | VarStore: PchSetup | VarOffset: 0x149 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
NFER | VarStore: PchSetup | VarOffset: 0x161 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
CER | VarStore: PchSetup | VarOffset: 0x179 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
CTO | VarStore: PchSetup | VarOffset: 0x191 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
SEFE | VarStore: PchSetup | VarOffset: 0x1C1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
SENFE | VarStore: PchSetup | VarOffset: 0x1D9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
SECE | VarStore: PchSetup | VarOffset: 0x1F1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
PME SCI | VarStore: PchSetup | VarOffset: 0x209 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
Hot Plug | VarStore: PchSetup | VarOffset: 0x221 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x239 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
PCIe Speed | VarStore: PchSetup | VarOffset: 0x251 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 12
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x269 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
Detect Timeout | VarStore: PchSetup | VarOffset: 0x3AC | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 12
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x502 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 12
Reserved Memory | VarStore: PchSetup | VarOffset: 0x525 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 12
Reserved I/O | VarStore: PchSetup | VarOffset: 0x54A | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 12
LTR | VarStore: PchSetup | VarOffset: 0x3F9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x429 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 12
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x494 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 12
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x441 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 12
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x459 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 12
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4C4 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 12
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x471 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 12
Force LTR Override | VarStore: PchSetup | VarOffset: 0x4E9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 12
LTR Lock | VarStore: PchSetup | VarOffset: 0x411 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
PCI Express Root Port 13 | VarStore: PchSetup | VarOffset: 0x102 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
Disable Gen2 Pll Shutdown and L1 Controller Power gating | VarStore: PchSetup | VarOffset: 0x3D3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
Connection Type | VarStore: PchSetup | VarOffset: 0x38A | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 13
ASPM 12 | VarStore: PchSetup | VarOffset: 0x11A | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 13
L1 SubStates | VarStore: PchSetup | VarOffset: 0x282 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 13
Gen3 Eq Phase3 Method | VarStore: PchSetup | VarOffset: 0x2FA | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 13
UPTP | VarStore: PchSetup | VarOffset: 0x312 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 13
DPTP | VarStore: PchSetup | VarOffset: 0x32A | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 13
ACS | VarStore: PchSetup | VarOffset: 0x29A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
PTM | VarStore: PchSetup | VarOffset: 0x2B2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
DPC | VarStore: PchSetup | VarOffset: 0x2CA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
EDPC | VarStore: PchSetup | VarOffset: 0x2E2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
URR | VarStore: PchSetup | VarOffset: 0x132 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
FER | VarStore: PchSetup | VarOffset: 0x14A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
NFER | VarStore: PchSetup | VarOffset: 0x162 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
CER | VarStore: PchSetup | VarOffset: 0x17A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
CTO | VarStore: PchSetup | VarOffset: 0x192 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
SEFE | VarStore: PchSetup | VarOffset: 0x1C2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
SENFE | VarStore: PchSetup | VarOffset: 0x1DA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
SECE | VarStore: PchSetup | VarOffset: 0x1F2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
PME SCI | VarStore: PchSetup | VarOffset: 0x20A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
Hot Plug | VarStore: PchSetup | VarOffset: 0x222 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x23A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
PCIe Speed | VarStore: PchSetup | VarOffset: 0x252 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 13
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x26A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
Detect Timeout | VarStore: PchSetup | VarOffset: 0x3AE | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 13
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x503 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 13
Reserved Memory | VarStore: PchSetup | VarOffset: 0x527 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 13
Reserved I/O | VarStore: PchSetup | VarOffset: 0x54B | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 13
LTR | VarStore: PchSetup | VarOffset: 0x3FA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x42A | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 13
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x496 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 13
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x442 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 13
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x45A | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 13
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4C6 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 13
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x472 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 13
Force LTR Override | VarStore: PchSetup | VarOffset: 0x4EA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 13
LTR Lock | VarStore: PchSetup | VarOffset: 0x412 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
PCI Express Root Port 14 | VarStore: PchSetup | VarOffset: 0x103 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
Disable Gen2 Pll Shutdown and L1 Controller Power gating | VarStore: PchSetup | VarOffset: 0x3D4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
Connection Type | VarStore: PchSetup | VarOffset: 0x38B | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 14
ASPM 13 | VarStore: PchSetup | VarOffset: 0x11B | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 14
L1 SubStates | VarStore: PchSetup | VarOffset: 0x283 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 14
Gen3 Eq Phase3 Method | VarStore: PchSetup | VarOffset: 0x2FB | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 14
UPTP | VarStore: PchSetup | VarOffset: 0x313 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 14
DPTP | VarStore: PchSetup | VarOffset: 0x32B | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 14
ACS | VarStore: PchSetup | VarOffset: 0x29B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
PTM | VarStore: PchSetup | VarOffset: 0x2B3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
DPC | VarStore: PchSetup | VarOffset: 0x2CB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
EDPC | VarStore: PchSetup | VarOffset: 0x2E3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
URR | VarStore: PchSetup | VarOffset: 0x133 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
FER | VarStore: PchSetup | VarOffset: 0x14B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
NFER | VarStore: PchSetup | VarOffset: 0x163 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
CER | VarStore: PchSetup | VarOffset: 0x17B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
CTO | VarStore: PchSetup | VarOffset: 0x193 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
SEFE | VarStore: PchSetup | VarOffset: 0x1C3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
SENFE | VarStore: PchSetup | VarOffset: 0x1DB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
SECE | VarStore: PchSetup | VarOffset: 0x1F3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
PME SCI | VarStore: PchSetup | VarOffset: 0x20B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
Hot Plug | VarStore: PchSetup | VarOffset: 0x223 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x23B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
PCIe Speed | VarStore: PchSetup | VarOffset: 0x253 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 14
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x26B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
Detect Timeout | VarStore: PchSetup | VarOffset: 0x3B0 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 14
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x504 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 14
Reserved Memory | VarStore: PchSetup | VarOffset: 0x529 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 14
Reserved I/O | VarStore: PchSetup | VarOffset: 0x54C | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 14
LTR | VarStore: PchSetup | VarOffset: 0x3FB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x42B | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 14
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x498 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 14
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x443 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 14
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x45B | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 14
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4C8 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 14
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x473 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 14
Force LTR Override | VarStore: PchSetup | VarOffset: 0x4EB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 14
LTR Lock | VarStore: PchSetup | VarOffset: 0x413 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
PCI Express Root Port 15 | VarStore: PchSetup | VarOffset: 0x104 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
Disable Gen2 Pll Shutdown and L1 Controller Power gating | VarStore: PchSetup | VarOffset: 0x3D5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
Connection Type | VarStore: PchSetup | VarOffset: 0x38C | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 15
ASPM 14 | VarStore: PchSetup | VarOffset: 0x11C | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 15
L1 SubStates | VarStore: PchSetup | VarOffset: 0x284 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 15
Gen3 Eq Phase3 Method | VarStore: PchSetup | VarOffset: 0x2FC | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 15
UPTP | VarStore: PchSetup | VarOffset: 0x314 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 15
DPTP | VarStore: PchSetup | VarOffset: 0x32C | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 15
ACS | VarStore: PchSetup | VarOffset: 0x29C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
PTM | VarStore: PchSetup | VarOffset: 0x2B4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
DPC | VarStore: PchSetup | VarOffset: 0x2CC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
EDPC | VarStore: PchSetup | VarOffset: 0x2E4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
URR | VarStore: PchSetup | VarOffset: 0x134 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
FER | VarStore: PchSetup | VarOffset: 0x14C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
NFER | VarStore: PchSetup | VarOffset: 0x164 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
CER | VarStore: PchSetup | VarOffset: 0x17C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
CTO | VarStore: PchSetup | VarOffset: 0x194 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
SEFE | VarStore: PchSetup | VarOffset: 0x1C4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
SENFE | VarStore: PchSetup | VarOffset: 0x1DC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
SECE | VarStore: PchSetup | VarOffset: 0x1F4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
PME SCI | VarStore: PchSetup | VarOffset: 0x20C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
Hot Plug | VarStore: PchSetup | VarOffset: 0x224 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x23C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
PCIe Speed | VarStore: PchSetup | VarOffset: 0x254 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 15
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x26C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
Detect Timeout | VarStore: PchSetup | VarOffset: 0x3B2 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 15
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x505 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 15
Reserved Memory | VarStore: PchSetup | VarOffset: 0x52B | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 15
Reserved I/O | VarStore: PchSetup | VarOffset: 0x54D | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 15
LTR | VarStore: PchSetup | VarOffset: 0x3FC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x42C | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 15
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x49A | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 15
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x444 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 15
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x45C | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 15
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4CA | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 15
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x474 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 15
Force LTR Override | VarStore: PchSetup | VarOffset: 0x4EC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 15
LTR Lock | VarStore: PchSetup | VarOffset: 0x414 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 16
PCI Express Root Port 16 | VarStore: PchSetup | VarOffset: 0x105 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 16
Disable Gen2 Pll Shutdown and L1 Controller Power gating | VarStore: PchSetup | VarOffset: 0x3D6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 16
Connection Type | VarStore: PchSetup | VarOffset: 0x38D | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 16
ASPM 15 | VarStore: PchSetup | VarOffset: 0x11D | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 16
L1 SubStates | VarStore: PchSetup | VarOffset: 0x285 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 16
Gen3 Eq Phase3 Method | VarStore: PchSetup | VarOffset: 0x2FD | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 16
UPTP | VarStore: PchSetup | VarOffset: 0x315 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 16
DPTP | VarStore: PchSetup | VarOffset: 0x32D | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 16
ACS | VarStore: PchSetup | VarOffset: 0x29D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 16
PTM | VarStore: PchSetup | VarOffset: 0x2B5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 16
DPC | VarStore: PchSetup | VarOffset: 0x2CD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 16
EDPC | VarStore: PchSetup | VarOffset: 0x2E5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 16
URR | VarStore: PchSetup | VarOffset: 0x135 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 16
FER | VarStore: PchSetup | VarOffset: 0x14D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 16
NFER | VarStore: PchSetup | VarOffset: 0x165 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 16
CER | VarStore: PchSetup | VarOffset: 0x17D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 16
CTO | VarStore: PchSetup | VarOffset: 0x195 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 16
SEFE | VarStore: PchSetup | VarOffset: 0x1C5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 16
SENFE | VarStore: PchSetup | VarOffset: 0x1DD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 16
SECE | VarStore: PchSetup | VarOffset: 0x1F5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 16
PME SCI | VarStore: PchSetup | VarOffset: 0x20D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 16
Hot Plug | VarStore: PchSetup | VarOffset: 0x225 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 16
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x23D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 16
PCIe Speed | VarStore: PchSetup | VarOffset: 0x255 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 16
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x26D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 16
Detect Timeout | VarStore: PchSetup | VarOffset: 0x3B4 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 16
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x506 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 16
Reserved Memory | VarStore: PchSetup | VarOffset: 0x52D | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 16
Reserved I/O | VarStore: PchSetup | VarOffset: 0x54E | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 16
LTR | VarStore: PchSetup | VarOffset: 0x3FD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 16
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x42D | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 16
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x49C | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 16
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x445 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 16
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x45D | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 16
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4CC | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 16
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x475 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 16
Force LTR Override | VarStore: PchSetup | VarOffset: 0x4ED | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 16
LTR Lock | VarStore: PchSetup | VarOffset: 0x415 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-M1
PCI Express Root Port 17 | VarStore: PchSetup | VarOffset: 0x106 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-M1
Disable Gen2 Pll Shutdown and L1 Controller Power gating | VarStore: PchSetup | VarOffset: 0x3D7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-M1
Connection Type | VarStore: PchSetup | VarOffset: 0x38E | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI-E M.2-M1
M.2-M1 ASPM | VarStore: PchSetup | VarOffset: 0x11E | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI-E M.2-M1
M.2-M1 L1 Substates | VarStore: PchSetup | VarOffset: 0x286 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI-E M.2-M1
Gen3 Eq Phase3 Method | VarStore: PchSetup | VarOffset: 0x2FE | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI-E M.2-M1
UPTP | VarStore: PchSetup | VarOffset: 0x316 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI-E M.2-M1
DPTP | VarStore: PchSetup | VarOffset: 0x32E | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI-E M.2-M1
ACS | VarStore: PchSetup | VarOffset: 0x29E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-M1
PTM | VarStore: PchSetup | VarOffset: 0x2B6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-M1
DPC | VarStore: PchSetup | VarOffset: 0x2CE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-M1
EDPC | VarStore: PchSetup | VarOffset: 0x2E6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-M1
URR | VarStore: PchSetup | VarOffset: 0x136 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-M1
FER | VarStore: PchSetup | VarOffset: 0x14E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-M1
NFER | VarStore: PchSetup | VarOffset: 0x166 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-M1
CER | VarStore: PchSetup | VarOffset: 0x17E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-M1
CTO | VarStore: PchSetup | VarOffset: 0x196 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-M1
SEFE | VarStore: PchSetup | VarOffset: 0x1C6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-M1
SENFE | VarStore: PchSetup | VarOffset: 0x1DE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-M1
SECE | VarStore: PchSetup | VarOffset: 0x1F6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-M1
PME SCI | VarStore: PchSetup | VarOffset: 0x20E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-M1
Hot Plug | VarStore: PchSetup | VarOffset: 0x226 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-M1
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x23E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-M1
PCIe Speed | VarStore: PchSetup | VarOffset: 0x256 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI-E M.2-M1
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x26E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-M1
Detect Timeout | VarStore: PchSetup | VarOffset: 0x3B6 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI-E M.2-M1
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x507 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI-E M.2-M1
Reserved Memory | VarStore: PchSetup | VarOffset: 0x52F | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI-E M.2-M1
Reserved I/O | VarStore: PchSetup | VarOffset: 0x54F | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI-E M.2-M1
LTR | VarStore: PchSetup | VarOffset: 0x3FE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-M1
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x42E | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI-E M.2-M1
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x49E | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI-E M.2-M1
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x446 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI-E M.2-M1
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x45E | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI-E M.2-M1
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4CE | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI-E M.2-M1
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x476 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI-E M.2-M1
Force LTR Override | VarStore: PchSetup | VarOffset: 0x4EE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI-E M.2-M1
LTR Lock | VarStore: PchSetup | VarOffset: 0x416 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 18
PCI Express Root Port 18 | VarStore: PchSetup | VarOffset: 0x107 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 18
Disable Gen2 Pll Shutdown and L1 Controller Power gating | VarStore: PchSetup | VarOffset: 0x3D8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 18
Connection Type | VarStore: PchSetup | VarOffset: 0x38F | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 18
ASPM 17 | VarStore: PchSetup | VarOffset: 0x11F | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 18
L1 SubStates | VarStore: PchSetup | VarOffset: 0x287 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 18
Gen3 Eq Phase3 Method | VarStore: PchSetup | VarOffset: 0x2FF | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 18
UPTP | VarStore: PchSetup | VarOffset: 0x317 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 18
DPTP | VarStore: PchSetup | VarOffset: 0x32F | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 18
ACS | VarStore: PchSetup | VarOffset: 0x29F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 18
PTM | VarStore: PchSetup | VarOffset: 0x2B7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 18
DPC | VarStore: PchSetup | VarOffset: 0x2CF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 18
EDPC | VarStore: PchSetup | VarOffset: 0x2E7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 18
URR | VarStore: PchSetup | VarOffset: 0x137 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 18
FER | VarStore: PchSetup | VarOffset: 0x14F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 18
NFER | VarStore: PchSetup | VarOffset: 0x167 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 18
CER | VarStore: PchSetup | VarOffset: 0x17F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 18
CTO | VarStore: PchSetup | VarOffset: 0x197 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 18
SEFE | VarStore: PchSetup | VarOffset: 0x1C7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 18
SENFE | VarStore: PchSetup | VarOffset: 0x1DF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 18
SECE | VarStore: PchSetup | VarOffset: 0x1F7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 18
PME SCI | VarStore: PchSetup | VarOffset: 0x20F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 18
Hot Plug | VarStore: PchSetup | VarOffset: 0x227 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 18
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x23F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 18
PCIe Speed | VarStore: PchSetup | VarOffset: 0x257 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 18
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x26F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 18
Detect Timeout | VarStore: PchSetup | VarOffset: 0x3B8 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 18
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x508 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 18
Reserved Memory | VarStore: PchSetup | VarOffset: 0x531 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 18
Reserved I/O | VarStore: PchSetup | VarOffset: 0x550 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 18
LTR | VarStore: PchSetup | VarOffset: 0x3FF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 18
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x42F | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 18
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4A0 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 18
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x447 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 18
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x45F | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 18
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4D0 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 18
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x477 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 18
Force LTR Override | VarStore: PchSetup | VarOffset: 0x4EF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 18
LTR Lock | VarStore: PchSetup | VarOffset: 0x417 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 19
PCI Express Root Port 19 | VarStore: PchSetup | VarOffset: 0x108 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 19
Disable Gen2 Pll Shutdown and L1 Controller Power gating | VarStore: PchSetup | VarOffset: 0x3D9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 19
Connection Type | VarStore: PchSetup | VarOffset: 0x390 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 19
ASPM 18 | VarStore: PchSetup | VarOffset: 0x120 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 19
L1 SubStates | VarStore: PchSetup | VarOffset: 0x288 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 19
Gen3 Eq Phase3 Method | VarStore: PchSetup | VarOffset: 0x300 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 19
UPTP | VarStore: PchSetup | VarOffset: 0x318 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 19
DPTP | VarStore: PchSetup | VarOffset: 0x330 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 19
ACS | VarStore: PchSetup | VarOffset: 0x2A0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 19
PTM | VarStore: PchSetup | VarOffset: 0x2B8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 19
DPC | VarStore: PchSetup | VarOffset: 0x2D0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 19
EDPC | VarStore: PchSetup | VarOffset: 0x2E8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 19
URR | VarStore: PchSetup | VarOffset: 0x138 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 19
FER | VarStore: PchSetup | VarOffset: 0x150 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 19
NFER | VarStore: PchSetup | VarOffset: 0x168 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 19
CER | VarStore: PchSetup | VarOffset: 0x180 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 19
CTO | VarStore: PchSetup | VarOffset: 0x198 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 19
SEFE | VarStore: PchSetup | VarOffset: 0x1C8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 19
SENFE | VarStore: PchSetup | VarOffset: 0x1E0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 19
SECE | VarStore: PchSetup | VarOffset: 0x1F8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 19
PME SCI | VarStore: PchSetup | VarOffset: 0x210 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 19
Hot Plug | VarStore: PchSetup | VarOffset: 0x228 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 19
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x240 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 19
PCIe Speed | VarStore: PchSetup | VarOffset: 0x258 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 19
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x270 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 19
Detect Timeout | VarStore: PchSetup | VarOffset: 0x3BA | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 19
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x509 | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 19
Reserved Memory | VarStore: PchSetup | VarOffset: 0x533 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 19
Reserved I/O | VarStore: PchSetup | VarOffset: 0x551 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 19
LTR | VarStore: PchSetup | VarOffset: 0x400 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 19
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x430 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 19
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4A2 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 19
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x448 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 19
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x460 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 19
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4D2 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 19
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x478 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 19
Force LTR Override | VarStore: PchSetup | VarOffset: 0x4F0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 19
LTR Lock | VarStore: PchSetup | VarOffset: 0x418 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 20
PCI Express Root Port 20 | VarStore: PchSetup | VarOffset: 0x109 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 20
Disable Gen2 Pll Shutdown and L1 Controller Power gating | VarStore: PchSetup | VarOffset: 0x3DA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 20
Connection Type | VarStore: PchSetup | VarOffset: 0x391 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 20
ASPM 19 | VarStore: PchSetup | VarOffset: 0x121 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 20
L1 SubStates | VarStore: PchSetup | VarOffset: 0x289 | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 20
Gen3 Eq Phase3 Method | VarStore: PchSetup | VarOffset: 0x301 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 20
UPTP | VarStore: PchSetup | VarOffset: 0x319 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 20
DPTP | VarStore: PchSetup | VarOffset: 0x331 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 20
ACS | VarStore: PchSetup | VarOffset: 0x2A1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 20
PTM | VarStore: PchSetup | VarOffset: 0x2B9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 20
DPC | VarStore: PchSetup | VarOffset: 0x2D1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 20
EDPC | VarStore: PchSetup | VarOffset: 0x2E9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 20
URR | VarStore: PchSetup | VarOffset: 0x139 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 20
FER | VarStore: PchSetup | VarOffset: 0x151 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 20
NFER | VarStore: PchSetup | VarOffset: 0x169 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 20
CER | VarStore: PchSetup | VarOffset: 0x181 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 20
CTO | VarStore: PchSetup | VarOffset: 0x199 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 20
SEFE | VarStore: PchSetup | VarOffset: 0x1C9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 20
SENFE | VarStore: PchSetup | VarOffset: 0x1E1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 20
SECE | VarStore: PchSetup | VarOffset: 0x1F9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 20
PME SCI | VarStore: PchSetup | VarOffset: 0x211 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 20
Hot Plug | VarStore: PchSetup | VarOffset: 0x229 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 20
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x241 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 20
PCIe Speed | VarStore: PchSetup | VarOffset: 0x259 | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 20
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x271 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 20
Detect Timeout | VarStore: PchSetup | VarOffset: 0x3BC | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 20
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x50A | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 20
Reserved Memory | VarStore: PchSetup | VarOffset: 0x535 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 20
Reserved I/O | VarStore: PchSetup | VarOffset: 0x552 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 20
LTR | VarStore: PchSetup | VarOffset: 0x401 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 20
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x431 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 20
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4A4 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 20
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x449 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 20
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x461 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 20
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4D4 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 20
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x479 | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 20
Force LTR Override | VarStore: PchSetup | VarOffset: 0x4F1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 20
LTR Lock | VarStore: PchSetup | VarOffset: 0x419 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT7 PCI-E 3.0 X4
PCI Express Root Port 21 | VarStore: PchSetup | VarOffset: 0x10A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT7 PCI-E 3.0 X4
Disable Gen2 Pll Shutdown and L1 Controller Power gating | VarStore: PchSetup | VarOffset: 0x3DB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT7 PCI-E 3.0 X4
Connection Type | VarStore: PchSetup | VarOffset: 0x392 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCH SLOT7 PCI-E 3.0 X4
SLOT7 ASPM | VarStore: PchSetup | VarOffset: 0x122 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCH SLOT7 PCI-E 3.0 X4
SLOT7 L1 Substates | VarStore: PchSetup | VarOffset: 0x28A | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCH SLOT7 PCI-E 3.0 X4
Gen3 Eq Phase3 Method | VarStore: PchSetup | VarOffset: 0x302 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCH SLOT7 PCI-E 3.0 X4
UPTP | VarStore: PchSetup | VarOffset: 0x31A | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCH SLOT7 PCI-E 3.0 X4
DPTP | VarStore: PchSetup | VarOffset: 0x332 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCH SLOT7 PCI-E 3.0 X4
ACS | VarStore: PchSetup | VarOffset: 0x2A2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT7 PCI-E 3.0 X4
PTM | VarStore: PchSetup | VarOffset: 0x2BA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT7 PCI-E 3.0 X4
DPC | VarStore: PchSetup | VarOffset: 0x2D2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT7 PCI-E 3.0 X4
EDPC | VarStore: PchSetup | VarOffset: 0x2EA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT7 PCI-E 3.0 X4
URR | VarStore: PchSetup | VarOffset: 0x13A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT7 PCI-E 3.0 X4
FER | VarStore: PchSetup | VarOffset: 0x152 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT7 PCI-E 3.0 X4
NFER | VarStore: PchSetup | VarOffset: 0x16A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT7 PCI-E 3.0 X4
CER | VarStore: PchSetup | VarOffset: 0x182 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT7 PCI-E 3.0 X4
CTO | VarStore: PchSetup | VarOffset: 0x19A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT7 PCI-E 3.0 X4
SEFE | VarStore: PchSetup | VarOffset: 0x1CA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT7 PCI-E 3.0 X4
SENFE | VarStore: PchSetup | VarOffset: 0x1E2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT7 PCI-E 3.0 X4
SECE | VarStore: PchSetup | VarOffset: 0x1FA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT7 PCI-E 3.0 X4
PME SCI | VarStore: PchSetup | VarOffset: 0x212 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT7 PCI-E 3.0 X4
Hot Plug | VarStore: PchSetup | VarOffset: 0x22A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT7 PCI-E 3.0 X4
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x242 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT7 PCI-E 3.0 X4
PCIe Speed | VarStore: PchSetup | VarOffset: 0x25A | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCH SLOT7 PCI-E 3.0 X4
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x272 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT7 PCI-E 3.0 X4
Detect Timeout | VarStore: PchSetup | VarOffset: 0x3BE | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCH SLOT7 PCI-E 3.0 X4
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x50B | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCH SLOT7 PCI-E 3.0 X4
Reserved Memory | VarStore: PchSetup | VarOffset: 0x537 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCH SLOT7 PCI-E 3.0 X4
Reserved I/O | VarStore: PchSetup | VarOffset: 0x553 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCH SLOT7 PCI-E 3.0 X4
LTR | VarStore: PchSetup | VarOffset: 0x402 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT7 PCI-E 3.0 X4
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x432 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCH SLOT7 PCI-E 3.0 X4
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4A6 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCH SLOT7 PCI-E 3.0 X4
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x44A | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCH SLOT7 PCI-E 3.0 X4
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x462 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCH SLOT7 PCI-E 3.0 X4
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4D6 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCH SLOT7 PCI-E 3.0 X4
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x47A | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCH SLOT7 PCI-E 3.0 X4
Force LTR Override | VarStore: PchSetup | VarOffset: 0x4F2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCH SLOT7 PCI-E 3.0 X4
LTR Lock | VarStore: PchSetup | VarOffset: 0x41A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 22
PCI Express Root Port 22 | VarStore: PchSetup | VarOffset: 0x10B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 22
Disable Gen2 Pll Shutdown and L1 Controller Power gating | VarStore: PchSetup | VarOffset: 0x3DC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 22
Connection Type | VarStore: PchSetup | VarOffset: 0x393 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 22
ASPM 21 | VarStore: PchSetup | VarOffset: 0x123 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 22
L1 SubStates | VarStore: PchSetup | VarOffset: 0x28B | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 22
Gen3 Eq Phase3 Method | VarStore: PchSetup | VarOffset: 0x303 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 22
UPTP | VarStore: PchSetup | VarOffset: 0x31B | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 22
DPTP | VarStore: PchSetup | VarOffset: 0x333 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 22
ACS | VarStore: PchSetup | VarOffset: 0x2A3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 22
PTM | VarStore: PchSetup | VarOffset: 0x2BB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 22
DPC | VarStore: PchSetup | VarOffset: 0x2D3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 22
EDPC | VarStore: PchSetup | VarOffset: 0x2EB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 22
URR | VarStore: PchSetup | VarOffset: 0x13B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 22
FER | VarStore: PchSetup | VarOffset: 0x153 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 22
NFER | VarStore: PchSetup | VarOffset: 0x16B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 22
CER | VarStore: PchSetup | VarOffset: 0x183 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 22
CTO | VarStore: PchSetup | VarOffset: 0x19B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 22
SEFE | VarStore: PchSetup | VarOffset: 0x1CB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 22
SENFE | VarStore: PchSetup | VarOffset: 0x1E3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 22
SECE | VarStore: PchSetup | VarOffset: 0x1FB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 22
PME SCI | VarStore: PchSetup | VarOffset: 0x213 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 22
Hot Plug | VarStore: PchSetup | VarOffset: 0x22B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 22
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x243 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 22
PCIe Speed | VarStore: PchSetup | VarOffset: 0x25B | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 22
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x273 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 22
Detect Timeout | VarStore: PchSetup | VarOffset: 0x3C0 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 22
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x50C | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 22
Reserved Memory | VarStore: PchSetup | VarOffset: 0x539 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 22
Reserved I/O | VarStore: PchSetup | VarOffset: 0x554 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 22
LTR | VarStore: PchSetup | VarOffset: 0x403 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 22
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x433 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 22
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4A8 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 22
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x44B | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 22
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x463 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 22
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4D8 | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 22
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x47B | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 22
Force LTR Override | VarStore: PchSetup | VarOffset: 0x4F3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 22
LTR Lock | VarStore: PchSetup | VarOffset: 0x41B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 23
PCI Express Root Port 23 | VarStore: PchSetup | VarOffset: 0x10C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 23
Disable Gen2 Pll Shutdown and L1 Controller Power gating | VarStore: PchSetup | VarOffset: 0x3DD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 23
Connection Type | VarStore: PchSetup | VarOffset: 0x394 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 23
ASPM 22 | VarStore: PchSetup | VarOffset: 0x124 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 23
L1 SubStates | VarStore: PchSetup | VarOffset: 0x28C | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 23
Gen3 Eq Phase3 Method | VarStore: PchSetup | VarOffset: 0x304 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 23
UPTP | VarStore: PchSetup | VarOffset: 0x31C | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 23
DPTP | VarStore: PchSetup | VarOffset: 0x334 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 23
ACS | VarStore: PchSetup | VarOffset: 0x2A4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 23
PTM | VarStore: PchSetup | VarOffset: 0x2BC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 23
DPC | VarStore: PchSetup | VarOffset: 0x2D4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 23
EDPC | VarStore: PchSetup | VarOffset: 0x2EC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 23
URR | VarStore: PchSetup | VarOffset: 0x13C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 23
FER | VarStore: PchSetup | VarOffset: 0x154 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 23
NFER | VarStore: PchSetup | VarOffset: 0x16C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 23
CER | VarStore: PchSetup | VarOffset: 0x184 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 23
CTO | VarStore: PchSetup | VarOffset: 0x19C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 23
SEFE | VarStore: PchSetup | VarOffset: 0x1CC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 23
SENFE | VarStore: PchSetup | VarOffset: 0x1E4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 23
SECE | VarStore: PchSetup | VarOffset: 0x1FC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 23
PME SCI | VarStore: PchSetup | VarOffset: 0x214 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 23
Hot Plug | VarStore: PchSetup | VarOffset: 0x22C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 23
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x244 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 23
PCIe Speed | VarStore: PchSetup | VarOffset: 0x25C | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 23
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x274 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 23
Detect Timeout | VarStore: PchSetup | VarOffset: 0x3C2 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 23
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x50D | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 23
Reserved Memory | VarStore: PchSetup | VarOffset: 0x53B | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 23
Reserved I/O | VarStore: PchSetup | VarOffset: 0x555 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 23
LTR | VarStore: PchSetup | VarOffset: 0x404 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 23
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x434 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 23
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4AA | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 23
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x44C | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 23
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x464 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 23
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4DA | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 23
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x47C | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 23
Force LTR Override | VarStore: PchSetup | VarOffset: 0x4F4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 23
LTR Lock | VarStore: PchSetup | VarOffset: 0x41C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 24
PCI Express Root Port 24 | VarStore: PchSetup | VarOffset: 0x10D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 24
Disable Gen2 Pll Shutdown and L1 Controller Power gating | VarStore: PchSetup | VarOffset: 0x3DE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 24
Connection Type | VarStore: PchSetup | VarOffset: 0x395 | Size: 0x1
Built-in: 0x0
Slot: 0x1
PCI Express Root Port 24
ASPM 23 | VarStore: PchSetup | VarOffset: 0x125 | Size: 0x1
Disabled: 0x0
L0s: 0x1
L1: 0x2
L0sL1: 0x3
Auto: 0x4
PCI Express Root Port 24
L1 SubStates | VarStore: PchSetup | VarOffset: 0x28D | Size: 0x1
Disabled: 0x0
L1.1: 0x1
L1.1 & L1.2: 0x2
PCI Express Root Port 24
Gen3 Eq Phase3 Method | VarStore: PchSetup | VarOffset: 0x305 | Size: 0x1
Hardware: 0x1
Static Coeff.: 0x4
PCI Express Root Port 24
UPTP | VarStore: PchSetup | VarOffset: 0x31D | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 24
DPTP | VarStore: PchSetup | VarOffset: 0x335 | Size: 0x1
Min: 0x0 | Max: 0xA | Step: 0x1
PCI Express Root Port 24
ACS | VarStore: PchSetup | VarOffset: 0x2A5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 24
PTM | VarStore: PchSetup | VarOffset: 0x2BD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 24
DPC | VarStore: PchSetup | VarOffset: 0x2D5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 24
EDPC | VarStore: PchSetup | VarOffset: 0x2ED | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 24
URR | VarStore: PchSetup | VarOffset: 0x13D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 24
FER | VarStore: PchSetup | VarOffset: 0x155 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 24
NFER | VarStore: PchSetup | VarOffset: 0x16D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 24
CER | VarStore: PchSetup | VarOffset: 0x185 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 24
CTO | VarStore: PchSetup | VarOffset: 0x19D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 24
SEFE | VarStore: PchSetup | VarOffset: 0x1CD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 24
SENFE | VarStore: PchSetup | VarOffset: 0x1E5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 24
SECE | VarStore: PchSetup | VarOffset: 0x1FD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 24
PME SCI | VarStore: PchSetup | VarOffset: 0x215 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 24
Hot Plug | VarStore: PchSetup | VarOffset: 0x22D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 24
Advanced Error Reporting | VarStore: PchSetup | VarOffset: 0x245 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 24
PCIe Speed | VarStore: PchSetup | VarOffset: 0x25D | Size: 0x1
Auto: 0x0
Gen1: 0x1
Gen2: 0x2
Gen3: 0x3
PCI Express Root Port 24
Transmitter Half Swing | VarStore: PchSetup | VarOffset: 0x275 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 24
Detect Timeout | VarStore: PchSetup | VarOffset: 0x3C4 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
PCI Express Root Port 24
Extra Bus Reserved | VarStore: PchSetup | VarOffset: 0x50E | Size: 0x1
Min: 0x0 | Max: 0x7 | Step: 0x1
PCI Express Root Port 24
Reserved Memory | VarStore: PchSetup | VarOffset: 0x53D | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
PCI Express Root Port 24
Reserved I/O | VarStore: PchSetup | VarOffset: 0x556 | Size: 0x1
Min: 0x4 | Max: 0x14 | Step: 0x4
PCI Express Root Port 24
LTR | VarStore: PchSetup | VarOffset: 0x405 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 24
Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x435 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 24
Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4AC | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 24
Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x44D | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 24
Non Snoop Latency Override | VarStore: PchSetup | VarOffset: 0x465 | Size: 0x1
Disabled: 0x0
Manual: 0x1
Auto: 0x2
PCI Express Root Port 24
Non Snoop Latency Value | VarStore: PchSetup | VarOffset: 0x4DC | Size: 0x2
Min: 0x0 | Max: 0x3FF | Step: 0x1
PCI Express Root Port 24
Non Snoop Latency Multiplier | VarStore: PchSetup | VarOffset: 0x47D | Size: 0x1
1 ns: 0x0
32 ns: 0x1
1024 ns: 0x2
32768 ns: 0x3
1048576 ns: 0x4
33554432 ns: 0x5
PCI Express Root Port 24
Force LTR Override | VarStore: PchSetup | VarOffset: 0x4F5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
PCI Express Root Port 24
LTR Lock | VarStore: PchSetup | VarOffset: 0x41D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
Clock0 assignment | VarStore: PchSetup | VarOffset: 0xD6 | Size: 0x1
Platform-POR: 0x0
Enabled: 0x1
Disabled: 0x2
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
ClkReq for Clock0 | VarStore: PchSetup | VarOffset: 0xE6 | Size: 0x1
Platform-POR: 0x0
Disabled: 0xFF
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
Clock1 assignment | VarStore: PchSetup | VarOffset: 0xD7 | Size: 0x1
Platform-POR: 0x0
Enabled: 0x1
Disabled: 0x2
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
ClkReq for Clock1 | VarStore: PchSetup | VarOffset: 0xE7 | Size: 0x1
Platform-POR: 0x0
Disabled: 0xFF
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
Clock2 assignment | VarStore: PchSetup | VarOffset: 0xD8 | Size: 0x1
Platform-POR: 0x0
Enabled: 0x1
Disabled: 0x2
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
ClkReq for Clock2 | VarStore: PchSetup | VarOffset: 0xE8 | Size: 0x1
Platform-POR: 0x0
Disabled: 0xFF
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
Clock3 assignment | VarStore: PchSetup | VarOffset: 0xD9 | Size: 0x1
Platform-POR: 0x0
Enabled: 0x1
Disabled: 0x2
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
ClkReq for Clock3 | VarStore: PchSetup | VarOffset: 0xE9 | Size: 0x1
Platform-POR: 0x0
Disabled: 0xFF
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
Clock4 assignment | VarStore: PchSetup | VarOffset: 0xDA | Size: 0x1
Platform-POR: 0x0
Enabled: 0x1
Disabled: 0x2
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
ClkReq for Clock4 | VarStore: PchSetup | VarOffset: 0xEA | Size: 0x1
Platform-POR: 0x0
Disabled: 0xFF
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
Clock5 assignment | VarStore: PchSetup | VarOffset: 0xDB | Size: 0x1
Platform-POR: 0x0
Enabled: 0x1
Disabled: 0x2
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
ClkReq for Clock5 | VarStore: PchSetup | VarOffset: 0xEB | Size: 0x1
Platform-POR: 0x0
Disabled: 0xFF
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
Clock6 assignment | VarStore: PchSetup | VarOffset: 0xDC | Size: 0x1
Platform-POR: 0x0
Enabled: 0x1
Disabled: 0x2
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
ClkReq for Clock6 | VarStore: PchSetup | VarOffset: 0xEC | Size: 0x1
Platform-POR: 0x0
Disabled: 0xFF
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
Clock7 assignment | VarStore: PchSetup | VarOffset: 0xDD | Size: 0x1
Platform-POR: 0x0
Enabled: 0x1
Disabled: 0x2
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
ClkReq for Clock7 | VarStore: PchSetup | VarOffset: 0xED | Size: 0x1
Platform-POR: 0x0
Disabled: 0xFF
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
Clock8 assignment | VarStore: PchSetup | VarOffset: 0xDE | Size: 0x1
Platform-POR: 0x0
Enabled: 0x1
Disabled: 0x2
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
ClkReq for Clock8 | VarStore: PchSetup | VarOffset: 0xEE | Size: 0x1
Platform-POR: 0x0
Disabled: 0xFF
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
Clock9 assignment | VarStore: PchSetup | VarOffset: 0xDF | Size: 0x1
Platform-POR: 0x0
Enabled: 0x1
Disabled: 0x2
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
ClkReq for Clock9 | VarStore: PchSetup | VarOffset: 0xEF | Size: 0x1
Platform-POR: 0x0
Disabled: 0xFF
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
Clock10 assignment | VarStore: PchSetup | VarOffset: 0xE0 | Size: 0x1
Platform-POR: 0x0
Enabled: 0x1
Disabled: 0x2
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
ClkReq for Clock10 | VarStore: PchSetup | VarOffset: 0xF0 | Size: 0x1
Platform-POR: 0x0
Disabled: 0xFF
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
Clock11 assignment | VarStore: PchSetup | VarOffset: 0xE1 | Size: 0x1
Platform-POR: 0x0
Enabled: 0x1
Disabled: 0x2
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
ClkReq for Clock11 | VarStore: PchSetup | VarOffset: 0xF1 | Size: 0x1
Platform-POR: 0x0
Disabled: 0xFF
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
Clock12 assignment | VarStore: PchSetup | VarOffset: 0xE2 | Size: 0x1
Platform-POR: 0x0
Enabled: 0x1
Disabled: 0x2
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
ClkReq for Clock12 | VarStore: PchSetup | VarOffset: 0xF2 | Size: 0x1
Platform-POR: 0x0
Disabled: 0xFF
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
Clock13 assignment | VarStore: PchSetup | VarOffset: 0xE3 | Size: 0x1
Platform-POR: 0x0
Enabled: 0x1
Disabled: 0x2
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
ClkReq for Clock13 | VarStore: PchSetup | VarOffset: 0xF3 | Size: 0x1
Platform-POR: 0x0
Disabled: 0xFF
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
Clock14 assignment | VarStore: PchSetup | VarOffset: 0xE4 | Size: 0x1
Platform-POR: 0x0
Enabled: 0x1
Disabled: 0x2
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
ClkReq for Clock14 | VarStore: PchSetup | VarOffset: 0xF4 | Size: 0x1
Platform-POR: 0x0
Disabled: 0xFF
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
Clock15 assignment | VarStore: PchSetup | VarOffset: 0xE5 | Size: 0x1
Platform-POR: 0x0
Enabled: 0x1
Disabled: 0x2
Platform-POR = clock is assigned to PCIe port or LAN according to board layout. Enabled = keep clock enabledeven if unused. Disabled = Disable clock.
ClkReq for Clock15 | VarStore: PchSetup | VarOffset: 0xF5 | Size: 0x1
Platform-POR: 0x0
Disabled: 0xFF
HD Audio Configuration
HD Audio | VarStore: PchSetup | VarOffset: 0x557 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
HD Audio Configuration
Audio DSP | VarStore: PchSetup | VarOffset: 0x558 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
HD Audio Configuration
Audio DSP Compliance Mode | VarStore: PchSetup | VarOffset: 0x559 | Size: 0x1
Non-UAA (IntelSST): 0x0
UAA (HDA Inbox/IntelSST): 0x1
HD Audio Configuration
Audio Link Mode | VarStore: PchSetup | VarOffset: 0x55C | Size: 0x1
HD Audio Link: 0x0
SSP (I2S): 0x1
SoundWire: 0x2
Advanced Link Config: 0x3
HD Audio Configuration
HDA Link | VarStore: PchSetup | VarOffset: 0x55D
HD Audio Configuration
DMIC #0 | VarStore: PchSetup | VarOffset: 0x55E
HD Audio Configuration
DMIC #1 | VarStore: PchSetup | VarOffset: 0x55F
HD Audio Configuration
SSP #0 | VarStore: PchSetup | VarOffset: 0x560
HD Audio Configuration
SSP #1 | VarStore: PchSetup | VarOffset: 0x561
HD Audio Configuration
SSP #2 | VarStore: PchSetup | VarOffset: 0x562
HD Audio Configuration
SSP #3 | VarStore: PchSetup | VarOffset: 0x563
HD Audio Configuration
SSP #4 | VarStore: PchSetup | VarOffset: 0x564
HD Audio Configuration
SSP #5 | VarStore: PchSetup | VarOffset: 0x565
HD Audio Configuration
SNDW #1 | VarStore: PchSetup | VarOffset: 0x566
HD Audio Configuration
SNDW #2 | VarStore: PchSetup | VarOffset: 0x567
HD Audio Configuration
SNDW #3 | VarStore: PchSetup | VarOffset: 0x568
HD Audio Configuration
SNDW #4 | VarStore: PchSetup | VarOffset: 0x569
HD Audio Configuration
HDA-Link Codec Select | VarStore: PchSetup | VarOffset: 0x56F | Size: 0x1
Platform Onboard: 0x0
External Kit: 0x1
HD Audio Advanced Configuration
iDisplay Audio Disconnect | VarStore: PchSetup | VarOffset: 0x55A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
HD Audio Advanced Configuration
Codec Sx Wake Capability | VarStore: PchSetup | VarOffset: 0x56D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
HD Audio Advanced Configuration
PME Enable | VarStore: PchSetup | VarOffset: 0x55B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
HD Audio Advanced Configuration
SoundWire Buffer RCOMP Setting | VarStore: PchSetup | VarOffset: 0x56E | Size: 0x1
Non-ACT Topology: 0x0
ACT Topology: 0x1
HD Audio Advanced Configuration
HD Audio Link Frequency | VarStore: PchSetup | VarOffset: 0x56A | Size: 0x1
6 MHz: 0x0
12 MHz: 0x1
24 MHz: 0x2
HD Audio Advanced Configuration
iDisplay Audio Link Frequency | VarStore: PchSetup | VarOffset: 0x56B | Size: 0x1
48 MHz: 0x3
96 MHz: 0x4
HD Audio Advanced Configuration
iDisplay Audio Link T-Mode | VarStore: PchSetup | VarOffset: 0x56C | Size: 0x1
2T Mode: 0x0
1T Mode: 0x1
4T Mode: 0x2
8T Mode: 0x3
16T Mode: 0x4
HD Audio DSP Features Configuration
NHLT External Table | VarStore: PchSetup | VarOffset: 0x574 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
HD Audio DSP Features Configuration
DMIC | VarStore: PchSetup | VarOffset: 0x571 | Size: 0x1
Disabled: 0x0
1 Mic Array: 0x3
2 Mic Array: 0x1
4 Mic Array: 0x2
HD Audio DSP Features Configuration
Bluetooth | VarStore: PchSetup | VarOffset: 0x572 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
HD Audio DSP Features Configuration
I2S | VarStore: PchSetup | VarOffset: 0x573 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
HD Audio DSP Features Configuration
I2S Codec Select | VarStore: PchSetup | VarOffset: 0x570 | Size: 0x1
Disabled: 0x0
Realtek ALC274: 0x1
HD Audio DSP Features Configuration
WoV (Wake on Voice) | VarStore: PchSetup | VarOffset: 0x575
HD Audio DSP Features Configuration
Bluetooth Sideband | VarStore: PchSetup | VarOffset: 0x576
HD Audio DSP Features Configuration
BT Intel HFP | VarStore: PchSetup | VarOffset: 0x57A
HD Audio DSP Features Configuration
BT Intel A2DP | VarStore: PchSetup | VarOffset: 0x57B
HD Audio DSP Features Configuration
Codec based VAD | VarStore: PchSetup | VarOffset: 0x577
HD Audio DSP Features Configuration
DSP based Speech
Pre-Processing Disabled | VarStore: PchSetup | VarOffset: 0x57C
HD Audio DSP Features Configuration
Voice Activity Detection | VarStore: PchSetup | VarOffset: 0x57D | Size: 0x1
Intel Wake on Voice: 0x0
Windows 10 Voice Activation: 0x1
HD Audio DSP Features Configuration
Waves Post-process | VarStore: PchSetup | VarOffset: 0x57E
HD Audio DSP Features Configuration
DTS | VarStore: PchSetup | VarOffset: 0x57F
HD Audio DSP Features Configuration
IntelSST Speech | VarStore: PchSetup | VarOffset: 0x580
HD Audio DSP Features Configuration
Dolby | VarStore: PchSetup | VarOffset: 0x581
HD Audio DSP Features Configuration
Waves Pre-process | VarStore: PchSetup | VarOffset: 0x582
HD Audio DSP Features Configuration
Audyssey | VarStore: PchSetup | VarOffset: 0x583
HD Audio DSP Features Configuration
Maxim Smart AMP | VarStore: PchSetup | VarOffset: 0x584
HD Audio DSP Features Configuration
ForteMedia SAMSoft | VarStore: PchSetup | VarOffset: 0x585
HD Audio DSP Features Configuration
Intel WoV | VarStore: PchSetup | VarOffset: 0x586
HD Audio DSP Features Configuration
Sound Research IP | VarStore: PchSetup | VarOffset: 0x587
HD Audio DSP Features Configuration
Conexant Pre-Process | VarStore: PchSetup | VarOffset: 0x588
HD Audio DSP Features Configuration
Conexant Smart Amp | VarStore: PchSetup | VarOffset: 0x589
HD Audio DSP Features Configuration
Realtek Post-Process | VarStore: PchSetup | VarOffset: 0x58A
HD Audio DSP Features Configuration
Realtek Smart Amp | VarStore: PchSetup | VarOffset: 0x58B
HD Audio DSP Features Configuration
Icepower IP MFX sub module | VarStore: PchSetup | VarOffset: 0x58C
HD Audio DSP Features Configuration
Icepower IP EFX sub module | VarStore: PchSetup | VarOffset: 0x58D
HD Audio DSP Features Configuration
Icepower IP SFX sub module | VarStore: PchSetup | VarOffset: 0x58E
HD Audio DSP Features Configuration
Voice Preprocessing | VarStore: PchSetup | VarOffset: 0x58F
HD Audio DSP Features Configuration
Custom Module 'Alpha' | VarStore: PchSetup | VarOffset: 0x59B
HD Audio DSP Features Configuration
'Alpha' GUID:
HD Audio DSP Features Configuration
Custom Module 'Beta' | VarStore: PchSetup | VarOffset: 0x59C
HD Audio DSP Features Configuration
'Beta' GUID:
HD Audio DSP Features Configuration
Custom Module 'Gamma' | VarStore: PchSetup | VarOffset: 0x59D
HD Audio DSP Features Configuration
'Gamma' GUID:
Security Configuration
RTC Memory Lock | VarStore: PchSetup | VarOffset: 0x16 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Security Configuration
BIOS Lock | VarStore: PchSetup | VarOffset: 0x17 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Security Configuration
Force unlock on all GPIO pads | VarStore: PchSetup | VarOffset: 0x18 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SerialIo Configuration
I2C0 Controller | VarStore: PchSetup | VarOffset: 0x6A8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SerialIo Configuration
I2C1 Controller | VarStore: PchSetup | VarOffset: 0x6A9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SerialIo Configuration
I2C2 Controller | VarStore: PchSetup | VarOffset: 0x6AA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SerialIo Configuration
I2C3 Controller | VarStore: PchSetup | VarOffset: 0x6AB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SerialIo Configuration
I2C4 Controller | VarStore: PchSetup | VarOffset: 0x6AC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SerialIo Configuration
I2C5 Controller | VarStore: PchSetup | VarOffset: 0x6AD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SerialIo Configuration
SPI0 Controller | VarStore: PchSetup | VarOffset: 0x699 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SerialIo Configuration
SPI1 Controller | VarStore: PchSetup | VarOffset: 0x69A | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SerialIo Configuration
SPI2 Controller | VarStore: PchSetup | VarOffset: 0x69B | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SerialIo Configuration
UART0 Controller | VarStore: PchSetup | VarOffset: 0x69C | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Communication port (COM): 0x3
SerialIo Configuration
UART1 Controller | VarStore: PchSetup | VarOffset: 0x69D | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Communication port (COM): 0x3
SerialIo Configuration
UART2 Controller | VarStore: PchSetup | VarOffset: 0x69E | Size: 0x1
Disabled: 0x0
Communication port (COM): 0x3
Enabled: 0x1
SerialIo Configuration
GPIO IRQ Route | VarStore: PchSetup | VarOffset: 0x6B2 | Size: 0x1
IRQ14: 0xE
IRQ15: 0xF
SerialIo Configuration
WITT/MITT Test Device | VarStore: Setup | VarOffset: 0x2E5 | Size: 0x1
Disabled: 0x0
Enabled - I2C0: 0x1
Enabled - I2C1: 0x2
Enabled - I2C2: 0x3
Enabled - I2C3: 0x4
Enabled - I2C4: 0x5
Enabled - I2C5: 0x6
Enabled - SPI0: 0x7
Enabled - SPI1: 0x8
Enabled - SPI2: 0x9
SerialIo Configuration
WITT/MITT Device selection | VarStore: Setup | VarOffset: 0x2E6 | Size: 0x1
WITT: 0x0
MITT: 0x1
SerialIo Configuration
UART Test Device | VarStore: Setup | VarOffset: 0x2E7 | Size: 0x1
Disabled: 0x0
Enabled - UART0: 0x1
Enabled - UART1: 0x2
Enabled - UART2: 0x3
SerialIo Configuration
Additional Serial IO devices | VarStore: PchSetup | VarOffset: 0x6B6
SerialIo Configuration
SerialIO timing parameters | VarStore: Setup | VarOffset: 0x2EA
Serial IO I2C0 Settings
Connected device | VarStore: Setup | VarOffset: 0x2C3 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Serial IO I2C0 Settings
StandardSpeed SCL High | VarStore: Setup | VarOffset: 0x2EB | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C0 Settings
StandardSpeed SCL Low | VarStore: Setup | VarOffset: 0x2ED | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C0 Settings
StandardSpeed SDA Hold | VarStore: Setup | VarOffset: 0x2EF | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C0 Settings
FastSpeed SCL High | VarStore: Setup | VarOffset: 0x2F1 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C0 Settings
FastSpeed SCL Low | VarStore: Setup | VarOffset: 0x2F3 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C0 Settings
FastSpeed SDA Hold | VarStore: Setup | VarOffset: 0x2F5 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C0 Settings
FastSpeedPlus SCL High | VarStore: Setup | VarOffset: 0x2F7 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C0 Settings
FastSpeedPlus SCL Low | VarStore: Setup | VarOffset: 0x2F9 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C0 Settings
FastSpeedPlus SDA Hold | VarStore: Setup | VarOffset: 0x2FB | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C0 Settings
HighSpeed SCL High | VarStore: Setup | VarOffset: 0x2FD | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C0 Settings
HighSpeed SCL Low | VarStore: Setup | VarOffset: 0x2FF | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C0 Settings
HighSpeed SDA Hold | VarStore: Setup | VarOffset: 0x301 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C0 Settings
D0->D3 idle timeout (screen off) | VarStore: Setup | VarOffset: 0x37B | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x0
Serial IO I2C0 Settings
D0->D3 idle timeout (screen on) | VarStore: Setup | VarOffset: 0x37D | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x0
Serial IO I2C1 Settings
Connected device | VarStore: Setup | VarOffset: 0x2C4 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Serial IO I2C1 Settings
StandardSpeed SCL High | VarStore: Setup | VarOffset: 0x303 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C1 Settings
StandardSpeed SCL Low | VarStore: Setup | VarOffset: 0x305 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C1 Settings
StandardSpeed SDA Hold | VarStore: Setup | VarOffset: 0x307 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C1 Settings
FastSpeed SCL High | VarStore: Setup | VarOffset: 0x309 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C1 Settings
FastSpeed SCL Low | VarStore: Setup | VarOffset: 0x30B | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C1 Settings
FastSpeed SDA Hold | VarStore: Setup | VarOffset: 0x30D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C1 Settings
FastSpeedPlus SCL High | VarStore: Setup | VarOffset: 0x30F | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C1 Settings
FastSpeedPlus SCL Low | VarStore: Setup | VarOffset: 0x311 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C1 Settings
FastSpeedPlus SDA Hold | VarStore: Setup | VarOffset: 0x313 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C1 Settings
HighSpeed SCL High | VarStore: Setup | VarOffset: 0x315 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C1 Settings
HighSpeed SCL Low | VarStore: Setup | VarOffset: 0x317 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C1 Settings
HighSpeed SDA Hold | VarStore: Setup | VarOffset: 0x319 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C1 Settings
D0->D3 idle timeout (screen off) | VarStore: Setup | VarOffset: 0x37F | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x0
Serial IO I2C1 Settings
D0->D3 idle timeout (screen on) | VarStore: Setup | VarOffset: 0x381 | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x0
Serial IO I2C2 Settings
Connected device | VarStore: Setup | VarOffset: 0x2C5 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Serial IO I2C2 Settings
StandardSpeed SCL High | VarStore: Setup | VarOffset: 0x31B | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C2 Settings
StandardSpeed SCL Low | VarStore: Setup | VarOffset: 0x31D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C2 Settings
StandardSpeed SDA Hold | VarStore: Setup | VarOffset: 0x31F | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C2 Settings
FastSpeed SCL High | VarStore: Setup | VarOffset: 0x321 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C2 Settings
FastSpeed SCL Low | VarStore: Setup | VarOffset: 0x323 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C2 Settings
FastSpeed SDA Hold | VarStore: Setup | VarOffset: 0x325 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C2 Settings
FastSpeedPlus SCL High | VarStore: Setup | VarOffset: 0x327 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C2 Settings
FastSpeedPlus SCL Low | VarStore: Setup | VarOffset: 0x329 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C2 Settings
FastSpeedPlus SDA Hold | VarStore: Setup | VarOffset: 0x32B | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C2 Settings
HighSpeed SCL High | VarStore: Setup | VarOffset: 0x32D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C2 Settings
HighSpeed SCL Low | VarStore: Setup | VarOffset: 0x32F | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C2 Settings
HighSpeed SDA Hold | VarStore: Setup | VarOffset: 0x331 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C2 Settings
D0->D3 idle timeout (screen off) | VarStore: Setup | VarOffset: 0x383 | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x0
Serial IO I2C2 Settings
D0->D3 idle timeout (screen on) | VarStore: Setup | VarOffset: 0x385 | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x0
Serial IO I2C3 Settings
Connected device | VarStore: Setup | VarOffset: 0x2C6 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Serial IO I2C3 Settings
StandardSpeed SCL High | VarStore: Setup | VarOffset: 0x333 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C3 Settings
StandardSpeed SCL Low | VarStore: Setup | VarOffset: 0x335 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C3 Settings
StandardSpeed SDA Hold | VarStore: Setup | VarOffset: 0x337 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C3 Settings
FastSpeed SCL High | VarStore: Setup | VarOffset: 0x339 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C3 Settings
FastSpeed SCL Low | VarStore: Setup | VarOffset: 0x33B | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C3 Settings
FastSpeed SDA Hold | VarStore: Setup | VarOffset: 0x33D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C3 Settings
FastSpeedPlus SCL High | VarStore: Setup | VarOffset: 0x33F | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C3 Settings
FastSpeedPlus SCL Low | VarStore: Setup | VarOffset: 0x341 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C3 Settings
FastSpeedPlus SDA Hold | VarStore: Setup | VarOffset: 0x343 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C3 Settings
HighSpeed SCL High | VarStore: Setup | VarOffset: 0x345 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C3 Settings
HighSpeed SCL Low | VarStore: Setup | VarOffset: 0x347 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C3 Settings
HighSpeed SDA Hold | VarStore: Setup | VarOffset: 0x349 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C3 Settings
D0->D3 idle timeout (screen off) | VarStore: Setup | VarOffset: 0x387 | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x0
Serial IO I2C3 Settings
D0->D3 idle timeout (screen on) | VarStore: Setup | VarOffset: 0x389 | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x0
Serial IO I2C4 Settings
StandardSpeed SCL High | VarStore: Setup | VarOffset: 0x34B | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C4 Settings
StandardSpeed SCL Low | VarStore: Setup | VarOffset: 0x34D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C4 Settings
StandardSpeed SDA Hold | VarStore: Setup | VarOffset: 0x34F | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C4 Settings
FastSpeed SCL High | VarStore: Setup | VarOffset: 0x351 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C4 Settings
FastSpeed SCL Low | VarStore: Setup | VarOffset: 0x353 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C4 Settings
FastSpeed SDA Hold | VarStore: Setup | VarOffset: 0x355 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C4 Settings
FastSpeedPlus SCL High | VarStore: Setup | VarOffset: 0x357 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C4 Settings
FastSpeedPlus SCL Low | VarStore: Setup | VarOffset: 0x359 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C4 Settings
FastSpeedPlus SDA Hold | VarStore: Setup | VarOffset: 0x35B | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C4 Settings
HighSpeed SCL High | VarStore: Setup | VarOffset: 0x35D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C4 Settings
HighSpeed SCL Low | VarStore: Setup | VarOffset: 0x35F | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C4 Settings
HighSpeed SDA Hold | VarStore: Setup | VarOffset: 0x361 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C4 Settings
D0->D3 idle timeout (screen off) | VarStore: Setup | VarOffset: 0x38B | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x0
Serial IO I2C4 Settings
D0->D3 idle timeout (screen on) | VarStore: Setup | VarOffset: 0x38D | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x0
Serial IO I2C5 Settings
StandardSpeed SCL High | VarStore: Setup | VarOffset: 0x363 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C5 Settings
StandardSpeed SCL Low | VarStore: Setup | VarOffset: 0x365 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C5 Settings
StandardSpeed SDA Hold | VarStore: Setup | VarOffset: 0x367 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C5 Settings
FastSpeed SCL High | VarStore: Setup | VarOffset: 0x369 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C5 Settings
FastSpeed SCL Low | VarStore: Setup | VarOffset: 0x36B | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C5 Settings
FastSpeed SDA Hold | VarStore: Setup | VarOffset: 0x36D | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C5 Settings
FastSpeedPlus SCL High | VarStore: Setup | VarOffset: 0x36F | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C5 Settings
FastSpeedPlus SCL Low | VarStore: Setup | VarOffset: 0x371 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C5 Settings
FastSpeedPlus SDA Hold | VarStore: Setup | VarOffset: 0x373 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C5 Settings
HighSpeed SCL High | VarStore: Setup | VarOffset: 0x375 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C5 Settings
HighSpeed SCL Low | VarStore: Setup | VarOffset: 0x377 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C5 Settings
HighSpeed SDA Hold | VarStore: Setup | VarOffset: 0x379 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Serial IO I2C5 Settings
D0->D3 idle timeout (screen off) | VarStore: Setup | VarOffset: 0x38F | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x0
Serial IO I2C5 Settings
D0->D3 idle timeout (screen on) | VarStore: Setup | VarOffset: 0x391 | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x0
Serial IO SPI0 Settings
ChipSelect 0 polarity | VarStore: PchSetup | VarOffset: 0x693 | Size: 0x1
Active Low: 0x0
Active High: 0x1
Serial IO SPI0 Settings
D0->D3 idle timeout (screen off) | VarStore: Setup | VarOffset: 0x393 | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x0
Serial IO SPI0 Settings
D0->D3 idle timeout (screen on) | VarStore: Setup | VarOffset: 0x395 | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x0
Serial IO SPI1 Settings
ChipSelect 0 polarity | VarStore: PchSetup | VarOffset: 0x695 | Size: 0x1
Active Low: 0x0
Active High: 0x1
Serial IO SPI1 Settings
Connected device | VarStore: Setup | VarOffset: 0x2D6 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Serial IO SPI2 Settings
ChipSelect 0 polarity | VarStore: PchSetup | VarOffset: 0x697 | Size: 0x1
Active Low: 0x0
Active High: 0x1
Serial IO SPI2 Settings
Connected device | VarStore: Setup | VarOffset: 0x2D7 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Serial IO UART0 Settings
Hardware Flow Control | VarStore: PchSetup | VarOffset: 0x6A2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Serial IO UART0 Settings
DMA Enable | VarStore: PchSetup | VarOffset: 0x69F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Serial IO UART0 Settings
Power Gating | VarStore: PchSetup | VarOffset: 0x6A5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Auto: 0x2
Serial IO UART0 Settings
D0->D3 idle timeout (screen off) | VarStore: Setup | VarOffset: 0x39F | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x0
Serial IO UART0 Settings
D0->D3 idle timeout (screen on) | VarStore: Setup | VarOffset: 0x3A1 | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x0
Serial IO UART1 Settings
Hardware Flow Control | VarStore: PchSetup | VarOffset: 0x6A3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Serial IO UART1 Settings
DMA Enable | VarStore: PchSetup | VarOffset: 0x6A0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Serial IO UART1 Settings
Power Gating | VarStore: PchSetup | VarOffset: 0x6A6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Auto: 0x2
Serial IO UART1 Settings
D0->D3 idle timeout (screen off) | VarStore: Setup | VarOffset: 0x3A3 | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x0
Serial IO UART1 Settings
D0->D3 idle timeout (screen on) | VarStore: Setup | VarOffset: 0x3A5 | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x0
Serial IO UART2 Settings
Hardware Flow Control | VarStore: PchSetup | VarOffset: 0x6A4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Serial IO UART2 Settings
DMA Enable | VarStore: PchSetup | VarOffset: 0x6A1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Serial IO UART2 Settings
Power Gating | VarStore: PchSetup | VarOffset: 0x6A7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Auto: 0x2
Serial IO UART2 Settings
D0->D3 idle timeout (screen off) | VarStore: Setup | VarOffset: 0x3A7 | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x0
Serial IO UART2 Settings
D0->D3 idle timeout (screen on) | VarStore: Setup | VarOffset: 0x3A9 | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x0
SCS Configuration
eMMC 5.0 Controller | VarStore: PchSetup | VarOffset: 0x67E | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SCS Configuration
Driver Strength | VarStore: PchSetup | VarOffset: 0x680 | Size: 0x1
33 Ohm: 0x0
40 Ohm: 0x1
50 Ohm: 0x2
SCS Configuration
eMMC 5.0 HS400 Mode | VarStore: PchSetup | VarOffset: 0x67F | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SCS Configuration
Enable HS400 software tuning | VarStore: PchSetup | VarOffset: 0x6EB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SCS Configuration
SDCard 3.0 Controller | VarStore: PchSetup | VarOffset: 0x681 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
SCS Configuration
UFS 2.0 Controller | VarStore: PchSetup | VarOffset: 0x682 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ISH Configuration
ISH Controller | VarStore: PchSetup | VarOffset: 0x683 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
ISH Configuration
PDT Unlock Message | VarStore: PchSetup | VarOffset: 0x692
ISH Configuration
SPI | VarStore: PchSetup | VarOffset: 0x684
ISH Configuration
UART0 | VarStore: PchSetup | VarOffset: 0x685
ISH Configuration
UART1 | VarStore: PchSetup | VarOffset: 0x686
ISH Configuration
I2C0 | VarStore: PchSetup | VarOffset: 0x687
ISH Configuration
I2C1 | VarStore: PchSetup | VarOffset: 0x688
ISH Configuration
I2C2 | VarStore: PchSetup | VarOffset: 0x689
ISH Configuration
GP_0 | VarStore: PchSetup | VarOffset: 0x68A
ISH Configuration
GP_1 | VarStore: PchSetup | VarOffset: 0x68B
ISH Configuration
GP_2 | VarStore: PchSetup | VarOffset: 0x68C
ISH Configuration
GP_3 | VarStore: PchSetup | VarOffset: 0x68D
ISH Configuration
GP_4 | VarStore: PchSetup | VarOffset: 0x68E
ISH Configuration
GP_5 | VarStore: PchSetup | VarOffset: 0x68F
ISH Configuration
GP_6 | VarStore: PchSetup | VarOffset: 0x690
ISH Configuration
GP_7 | VarStore: PchSetup | VarOffset: 0x691
Pch Thermal Throttling Control
Thermal Throttling Level | VarStore: PchSetup | VarOffset: 0x6BA | Size: 0x1
Suggested Setting: 0x1
Manual: 0x0
Pch Thermal Throttling Control
Thermal Throttling | VarStore: PchSetup | VarOffset: 0x6C1
Pch Thermal Throttling Control
TT State 13 | VarStore: PchSetup | VarOffset: 0x6C2
Pch Thermal Throttling Control
Thermal Throttling Lock | VarStore: PchSetup | VarOffset: 0x6C3
Pch Thermal Throttling Control
T0 Level | VarStore: PchSetup | VarOffset: 0x6BB | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Pch Thermal Throttling Control
T1 Level | VarStore: PchSetup | VarOffset: 0x6BD | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Pch Thermal Throttling Control
T2 Level | VarStore: PchSetup | VarOffset: 0x6BF | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Pch Thermal Throttling Control
DMI Thermal Setting | VarStore: PchSetup | VarOffset: 0x6C4 | Size: 0x1
Suggested Setting: 0x1
Manual: 0x0
Pch Thermal Throttling Control
DMI Thermal Sensor Autonomous Width | VarStore: PchSetup | VarOffset: 0x6C9
Pch Thermal Throttling Control
Thermal Sensor 0 Width | VarStore: PchSetup | VarOffset: 0x6C5 | Size: 0x1
x1: 0x0
x2: 0x1
x4: 0x2
x8: 0x3
x16: 0x4
Pch Thermal Throttling Control
Thermal Sensor 1 Width | VarStore: PchSetup | VarOffset: 0x6C6 | Size: 0x1
x1: 0x0
x2: 0x1
x4: 0x2
x8: 0x3
x16: 0x4
Pch Thermal Throttling Control
Thermal Sensor 2 Width | VarStore: PchSetup | VarOffset: 0x6C7 | Size: 0x1
x1: 0x0
x2: 0x1
x4: 0x2
x8: 0x3
x16: 0x4
Pch Thermal Throttling Control
Thermal Sensor 3 Width | VarStore: PchSetup | VarOffset: 0x6C8 | Size: 0x1
x1: 0x0
x2: 0x1
x4: 0x2
x8: 0x3
x16: 0x4
Pch Thermal Throttling Control
SATA Thermal Setting | VarStore: PchSetup | VarOffset: 0x6CA | Size: 0x1
Suggested Setting: 0x1
Manual: 0x0
Pch Thermal Throttling Control
T1 Multipler | VarStore: PchSetup | VarOffset: 0x6CB | Size: 0x1
Disabled: 0x0
x1: 0x1
x2: 0x2
x4: 0x3
Pch Thermal Throttling Control
T2 Multipler | VarStore: PchSetup | VarOffset: 0x6CC | Size: 0x1
Disabled: 0x0
x1: 0x1
x2: 0x2
x4: 0x3
Pch Thermal Throttling Control
T3 Multipler | VarStore: PchSetup | VarOffset: 0x6CD | Size: 0x1
Disabled: 0x0
x1: 0x1
x2: 0x2
x4: 0x3
Pch Thermal Throttling Control
Alternate Fast Init Tdispatch | VarStore: PchSetup | VarOffset: 0x6D0
Pch Thermal Throttling Control
Tdispatch | VarStore: PchSetup | VarOffset: 0x6CE | Size: 0x1
~32us: 0x0
~128us: 0x1
~8us: 0x3
~32ms: 0x0
~128ms: 0x1
~8ms: 0x3
Pch Thermal Throttling Control
Tinactive | VarStore: PchSetup | VarOffset: 0x6CF | Size: 0x1
~32us: 0x0
~128us: 0x1
~8us: 0x3
~32ms: 0x0
~128ms: 0x1
~8ms: 0x3
Pch Thermal Throttling Control
T1 Multipler | VarStore: PchSetup | VarOffset: 0x6D1 | Size: 0x1
Disabled: 0x0
x1: 0x1
x2: 0x2
x4: 0x3
Pch Thermal Throttling Control
T2 Multipler | VarStore: PchSetup | VarOffset: 0x6D2 | Size: 0x1
Disabled: 0x0
x1: 0x1
x2: 0x2
x4: 0x3
Pch Thermal Throttling Control
T3 Multipler | VarStore: PchSetup | VarOffset: 0x6D3 | Size: 0x1
Disabled: 0x0
x1: 0x1
x2: 0x2
x4: 0x3
Pch Thermal Throttling Control
Alternate Fast Init Tdispatch | VarStore: PchSetup | VarOffset: 0x6D6
Pch Thermal Throttling Control
Tdispatch | VarStore: PchSetup | VarOffset: 0x6D4 | Size: 0x1
~32us: 0x0
~128us: 0x1
~8us: 0x3
~32ms: 0x0
~128ms: 0x1
~8ms: 0x3
Pch Thermal Throttling Control
Tinactive | VarStore: PchSetup | VarOffset: 0x6D5 | Size: 0x1
~32us: 0x0
~128us: 0x1
~8us: 0x3
~32ms: 0x0
~128ms: 0x1
~8ms: 0x3
Serial IO Touch Pad Settings
Touch Pad | VarStore: Setup | VarOffset: 0x2C9 | Size: 0x1
Disabled: 0x0
Synaptics Precision Touchpad: 0x1
Synaptics Forcepad: 0x2
ALPS Precision Touchpad ClickPad: 0x6
Custom device: 0x5
Serial IO Touch Pad Settings
Touch Pad Interrupt Mode | VarStore: Setup | VarOffset: 0x2CA | Size: 0x1
GPIO Interrupt: 0x0
APIC Interrupt: 0x1
Serial IO Touch Pad Settings
Device's bus address | VarStore: Setup | VarOffset: 0x2CB | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Serial IO Touch Pad Settings
Device's HID address | VarStore: Setup | VarOffset: 0x2CC | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Serial IO Touch Pad Settings
Device's bus speed | VarStore: Setup | VarOffset: 0x2CE | Size: 0x1
100kHz: 0x0
400kHz: 0x1
1MHz: 0x2
Serial IO Touch Panel Settings
Touch Panel | VarStore: Setup | VarOffset: 0x2CF | Size: 0x1
Disabled: 0x0
Atmel3432 TouchPanel: 0x1
Atmel2952 TouchPanel: 0x2
Elan2097 TouchPanel: 0x3
N-Trig/Samsung 13.3": 0x4
N-Trig/Sharp 12.5": 0x5
WACOM TouchPanel: 0x6
Custom device: 0x7
Serial IO Touch Panel Settings
Touch Panel Interrupt Mode | VarStore: Setup | VarOffset: 0x2D0 | Size: 0x1
GPIO Interrupt: 0x0
APIC Interrupt: 0x1
Serial IO Touch Panel Settings
Device's bus address | VarStore: Setup | VarOffset: 0x2D1 | Size: 0x1
Min: 0x0 | Max: 0x7F | Step: 0x1
Serial IO Touch Panel Settings
Device's HID address | VarStore: Setup | VarOffset: 0x2D2 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x1
Serial IO Touch Panel Settings
Device's bus speed | VarStore: Setup | VarOffset: 0x2D4 | Size: 0x1
100kHz: 0x0
400kHz: 0x1
1MHz: 0x2
Serial IO Finger Print Settings
Finger Print Sensor | VarStore: Setup | VarOffset: 0x2E1 | Size: 0x1
Disabled: 0x0
FPC1011: 0x1
FPC1020: 0x2
VFSI6101: 0x3
Synaptics VFSI7500: 0x4
EGIS0300: 0x5
FPC1021: 0x6
Serial IO Finger Print Settings
Finger Print Interrupt Mode | VarStore: Setup | VarOffset: 0x2E2 | Size: 0x1
GPIO Interrupt: 0x0
APIC Interrupt: 0x1
Serial IO Finger Print Settings
D0->D3 idle timeout (screen off) | VarStore: Setup | VarOffset: 0x397 | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x0
Serial IO Finger Print Settings
D0->D3 idle timeout (screen on) | VarStore: Setup | VarOffset: 0x399 | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x0
Serial IO Finger Print Settings
D0->D3 idle timeout (screen off) | VarStore: Setup | VarOffset: 0x39B | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x0
Serial IO Finger Print Settings
D0->D3 idle timeout (screen on) | VarStore: Setup | VarOffset: 0x39D | Size: 0x2
Min: 0x1 | Max: 0x2710 | Step: 0x0
Extra options
Detect Non-Compliance Device | VarStore: Setup | VarOffset: 0x6F1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Extra options
Prefetchable Memory | VarStore: Setup | VarOffset: 0x709 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
Extra options
Reserved Memory Alignment | VarStore: Setup | VarOffset: 0x739 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Prefetchable Memory Alignment | VarStore: Setup | VarOffset: 0x751 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Detect Non-Compliance Device | VarStore: Setup | VarOffset: 0x6F2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Extra options
Prefetchable Memory | VarStore: Setup | VarOffset: 0x70B | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
Extra options
Reserved Memory Alignment | VarStore: Setup | VarOffset: 0x73A | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Prefetchable Memory Alignment | VarStore: Setup | VarOffset: 0x752 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Detect Non-Compliance Device | VarStore: Setup | VarOffset: 0x6F3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Extra options
Prefetchable Memory | VarStore: Setup | VarOffset: 0x70D | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
Extra options
Reserved Memory Alignment | VarStore: Setup | VarOffset: 0x73B | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Prefetchable Memory Alignment | VarStore: Setup | VarOffset: 0x753 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Detect Non-Compliance Device | VarStore: Setup | VarOffset: 0x6F4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Extra options
Prefetchable Memory | VarStore: Setup | VarOffset: 0x70F | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
Extra options
Reserved Memory Alignment | VarStore: Setup | VarOffset: 0x73C | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Prefetchable Memory Alignment | VarStore: Setup | VarOffset: 0x754 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Detect Non-Compliance Device | VarStore: Setup | VarOffset: 0x6F5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Extra options
Prefetchable Memory | VarStore: Setup | VarOffset: 0x711 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
Extra options
Reserved Memory Alignment | VarStore: Setup | VarOffset: 0x73D | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Prefetchable Memory Alignment | VarStore: Setup | VarOffset: 0x755 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Detect Non-Compliance Device | VarStore: Setup | VarOffset: 0x6F6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Extra options
Prefetchable Memory | VarStore: Setup | VarOffset: 0x713 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
Extra options
Reserved Memory Alignment | VarStore: Setup | VarOffset: 0x73E | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Prefetchable Memory Alignment | VarStore: Setup | VarOffset: 0x756 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Detect Non-Compliance Device | VarStore: Setup | VarOffset: 0x6F7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Extra options
Prefetchable Memory | VarStore: Setup | VarOffset: 0x715 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
Extra options
Reserved Memory Alignment | VarStore: Setup | VarOffset: 0x73F | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Prefetchable Memory Alignment | VarStore: Setup | VarOffset: 0x757 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Detect Non-Compliance Device | VarStore: Setup | VarOffset: 0x6F8 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Extra options
Prefetchable Memory | VarStore: Setup | VarOffset: 0x717 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
Extra options
Reserved Memory Alignment | VarStore: Setup | VarOffset: 0x740 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Prefetchable Memory Alignment | VarStore: Setup | VarOffset: 0x758 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Detect Non-Compliance Device | VarStore: Setup | VarOffset: 0x6F9 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Extra options
Prefetchable Memory | VarStore: Setup | VarOffset: 0x719 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
Extra options
Reserved Memory Alignment | VarStore: Setup | VarOffset: 0x741 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Prefetchable Memory Alignment | VarStore: Setup | VarOffset: 0x759 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Detect Non-Compliance Device | VarStore: Setup | VarOffset: 0x6FA | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Extra options
Prefetchable Memory | VarStore: Setup | VarOffset: 0x71B | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
Extra options
Reserved Memory Alignment | VarStore: Setup | VarOffset: 0x742 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Prefetchable Memory Alignment | VarStore: Setup | VarOffset: 0x75A | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Detect Non-Compliance Device | VarStore: Setup | VarOffset: 0x6FB | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Extra options
Prefetchable Memory | VarStore: Setup | VarOffset: 0x71D | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
Extra options
Reserved Memory Alignment | VarStore: Setup | VarOffset: 0x743 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Prefetchable Memory Alignment | VarStore: Setup | VarOffset: 0x75B | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Detect Non-Compliance Device | VarStore: Setup | VarOffset: 0x6FC | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Extra options
Prefetchable Memory | VarStore: Setup | VarOffset: 0x71F | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
Extra options
Reserved Memory Alignment | VarStore: Setup | VarOffset: 0x744 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Prefetchable Memory Alignment | VarStore: Setup | VarOffset: 0x75C | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Detect Non-Compliance Device | VarStore: Setup | VarOffset: 0x6FD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Extra options
Prefetchable Memory | VarStore: Setup | VarOffset: 0x721 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
Extra options
Reserved Memory Alignment | VarStore: Setup | VarOffset: 0x745 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Prefetchable Memory Alignment | VarStore: Setup | VarOffset: 0x75D | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Detect Non-Compliance Device | VarStore: Setup | VarOffset: 0x6FE | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Extra options
Prefetchable Memory | VarStore: Setup | VarOffset: 0x723 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
Extra options
Reserved Memory Alignment | VarStore: Setup | VarOffset: 0x746 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Prefetchable Memory Alignment | VarStore: Setup | VarOffset: 0x75E | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Detect Non-Compliance Device | VarStore: Setup | VarOffset: 0x6FF | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Extra options
Prefetchable Memory | VarStore: Setup | VarOffset: 0x725 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
Extra options
Reserved Memory Alignment | VarStore: Setup | VarOffset: 0x747 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Prefetchable Memory Alignment | VarStore: Setup | VarOffset: 0x75F | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Detect Non-Compliance Device | VarStore: Setup | VarOffset: 0x700 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Extra options
Prefetchable Memory | VarStore: Setup | VarOffset: 0x727 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
Extra options
Reserved Memory Alignment | VarStore: Setup | VarOffset: 0x748 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Prefetchable Memory Alignment | VarStore: Setup | VarOffset: 0x760 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Detect Non-Compliance Device | VarStore: Setup | VarOffset: 0x701 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Extra options
Prefetchable Memory | VarStore: Setup | VarOffset: 0x729 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
Extra options
Reserved Memory Alignment | VarStore: Setup | VarOffset: 0x749 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Prefetchable Memory Alignment | VarStore: Setup | VarOffset: 0x761 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Detect Non-Compliance Device | VarStore: Setup | VarOffset: 0x702 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Extra options
Prefetchable Memory | VarStore: Setup | VarOffset: 0x72B | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
Extra options
Reserved Memory Alignment | VarStore: Setup | VarOffset: 0x74A | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Prefetchable Memory Alignment | VarStore: Setup | VarOffset: 0x762 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Detect Non-Compliance Device | VarStore: Setup | VarOffset: 0x703 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Extra options
Prefetchable Memory | VarStore: Setup | VarOffset: 0x72D | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
Extra options
Reserved Memory Alignment | VarStore: Setup | VarOffset: 0x74B | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Prefetchable Memory Alignment | VarStore: Setup | VarOffset: 0x763 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Detect Non-Compliance Device | VarStore: Setup | VarOffset: 0x704 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Extra options
Prefetchable Memory | VarStore: Setup | VarOffset: 0x72F | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
Extra options
Reserved Memory Alignment | VarStore: Setup | VarOffset: 0x74C | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Prefetchable Memory Alignment | VarStore: Setup | VarOffset: 0x764 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Detect Non-Compliance Device | VarStore: Setup | VarOffset: 0x705 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Extra options
Prefetchable Memory | VarStore: Setup | VarOffset: 0x731 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
Extra options
Reserved Memory Alignment | VarStore: Setup | VarOffset: 0x74D | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Prefetchable Memory Alignment | VarStore: Setup | VarOffset: 0x765 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Detect Non-Compliance Device | VarStore: Setup | VarOffset: 0x706 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Extra options
Prefetchable Memory | VarStore: Setup | VarOffset: 0x733 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
Extra options
Reserved Memory Alignment | VarStore: Setup | VarOffset: 0x74E | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Prefetchable Memory Alignment | VarStore: Setup | VarOffset: 0x766 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Detect Non-Compliance Device | VarStore: Setup | VarOffset: 0x707 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Extra options
Prefetchable Memory | VarStore: Setup | VarOffset: 0x735 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
Extra options
Reserved Memory Alignment | VarStore: Setup | VarOffset: 0x74F | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Prefetchable Memory Alignment | VarStore: Setup | VarOffset: 0x767 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Detect Non-Compliance Device | VarStore: Setup | VarOffset: 0x708 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Extra options
Prefetchable Memory | VarStore: Setup | VarOffset: 0x737 | Size: 0x2
Min: 0x1 | Max: 0x14 | Step: 0x1
Extra options
Reserved Memory Alignment | VarStore: Setup | VarOffset: 0x750 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
Extra options
Prefetchable Memory Alignment | VarStore: Setup | VarOffset: 0x768 | Size: 0x1
Min: 0x1 | Max: 0x1F | Step: 0x1
PEG Port Feature Configuration
Detect Non-Compliance Device | VarStore: Setup | VarOffset: 0x7B2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
External Gfx Card Primary Display Configuration
Primary PEG | VarStore: Setup | VarOffset: 0x7B0 | Size: 0x1
Auto: 0x0
PEG11: 0x1
PEG12: 0x2
External Gfx Card Primary Display Configuration
Primary PCIE | VarStore: Setup | VarOffset: 0x7B1 | Size: 0x1
Auto: 0x0
PCH SLOT4 PCI-E 3.0 X4 (IN X8): 0x1
PCIE2: 0x2
PCIE3: 0x3
PCIE4: 0x4
PCIE5: 0x5
PCIE6: 0x6
PCIE7: 0x7
PCIE8: 0x8
PCIE9: 0x9
PCIE10: 0xA
PCIE11: 0xB
PCIE12: 0xC
PCIE13: 0xD
PCIE14: 0xE
PCIE15: 0xF
PCIE16: 0x10
PCIE17: 0x11
PCIE18: 0x12
PCIE19: 0x13
Security
Hard Drive Security Frozen | VarStore: Setup | VarOffset: 0x19 | Size: 0x1
Enabled: 0x1
Disabled: 0x0
Security
Password Check | VarStore: AMITSESetup | VarOffset: 0x50 | Size: 0x1
Setup: 0x0
Always: 0x1
Security
Lockdown Mode | VarStore: SmcDcmsSetup | VarOffset: 0x0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Security
System Lockdown Support | VarStore: SmcDcmsSetup | VarOffset: 0x2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Security
Sync Lockdown Flag | VarStore: SmcDcmsSetup | VarOffset: 0x1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Supermicro Secure Boot Configuration
Secure Boot Expose | VarStore: Setup | VarOffset: 0x17 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Supermicro Secure Boot Configuration
Secure Boot | VarStore: Setup | VarOffset: 0x15 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Supermicro Secure Boot Configuration
Reset Keys Type | VarStore: Setup | VarOffset: 0x16 | Size: 0x1
Disabled: 0x0
Reset all keys to default: 0x1
Delete all keys: 0x2
Delete PK key: 0x3
Supermicro Secure Boot Configuration
Secure Boot Mode | VarStore: Setup | VarOffset: 0x18 | Size: 0x1
Setup: 0x0
User: 0x1
Audit: 0x2
Deployed: 0x3
Secure Boot
Secure Boot | VarStore: SecureBootSetup | VarOffset: 0x0 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Secure Boot
Secure Boot Mode | VarStore: SecureBootSetup | VarOffset: 0x1 | Size: 0x1
Standard: 0x0
Custom: 0x1
Secure Boot
CSM Support | VarStore: Setup | VarOffset: 0x7E7 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Key Management
Factory Key Provision | VarStore: SecureBootSetup | VarOffset: 0x2 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Boot
Setup Prompt Timeout | VarStore: Timeout | VarOffset: 0x0 | Size: 0x2
Min: 0x1 | Max: 0xFFFF | Step: 0x1
Boot
Bootup NumLock State | VarStore: Setup | VarOffset: 0x0 | Size: 0x1
On: 0x1
Off: 0x0
Boot
Quiet Boot | VarStore: AMITSESetup | VarOffset: 0x51
Boot
Fast Boot | VarStore: Setup | VarOffset: 0x6BD | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Boot
SATA Support | VarStore: Setup | VarOffset: 0x6BE | Size: 0x1
Last Boot SATA Devices Only: 0x0
All SATA Devices: 0x1
Boot
NVMe Support | VarStore: Setup | VarOffset: 0x6C5 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Boot
UFS Support | VarStore: Setup | VarOffset: 0x6C6 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Boot
VGA Support | VarStore: Setup | VarOffset: 0x6BF | Size: 0x1
Auto: 0x0
EFI Driver: 0x1
Boot
USB Support | VarStore: Setup | VarOffset: 0x6C0 | Size: 0x1
Disabled: 0x0
Full Initial: 0x1
Partial Initial: 0x2
Boot
PS2 Devices Support | VarStore: Setup | VarOffset: 0x6C1 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Boot
Network Stack Driver Support | VarStore: Setup | VarOffset: 0x6C4 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Boot
Redirection Support | VarStore: Setup | VarOffset: 0x6C3 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Boot
Driver Option #%d | VarStore: DriverOrder | VarOffset: 0x0 | Size: 0x2
: 0x0
: 0x1
Boot
Boot Mode Select | VarStore: Setup | VarOffset: 0x7F3 | Size: 0x1
Legacy: 0x0
UEFI: 0x1
Dual: 0x2
Boot
LEGACY to EFI Support | VarStore: Setup | VarOffset: 0x874 | Size: 0x1
Disabled: 0x0
Enabled: 0x1
Boot
Boot Option #1 | VarStore: Setup | VarOffset: 0x814 | Size: 0x2
UEFI Hard Disk: 0x0
UEFI CD/DVD: 0x1
UEFI USB Hard Disk: 0x2
UEFI USB CD/DVD: 0x3
UEFI USB Key: 0x4
UEFI USB Floppy: 0x5
UEFI USB Lan: 0x6
UEFI Network: 0x7
UEFI AP: 0x8
Disabled: 0x9
Boot
Boot Option #2 | VarStore: Setup | VarOffset: 0x816 | Size: 0x2
UEFI Hard Disk: 0x0
UEFI CD/DVD: 0x1
UEFI USB Hard Disk: 0x2
UEFI USB CD/DVD: 0x3
UEFI USB Key: 0x4
UEFI USB Floppy: 0x5
UEFI USB Lan: 0x6
UEFI Network: 0x7
UEFI AP: 0x8
Disabled: 0x9
Boot
Boot Option #3 | VarStore: Setup | VarOffset: 0x818 | Size: 0x2
UEFI Hard Disk: 0x0
UEFI CD/DVD: 0x1
UEFI USB Hard Disk: 0x2
UEFI USB CD/DVD: 0x3
UEFI USB Key: 0x4
UEFI USB Floppy: 0x5
UEFI USB Lan: 0x6
UEFI Network: 0x7
UEFI AP: 0x8
Disabled: 0x9
Boot
Boot Option #4 | VarStore: Setup | VarOffset: 0x81A | Size: 0x2
UEFI Hard Disk: 0x0
UEFI CD/DVD: 0x1
UEFI USB Hard Disk: 0x2
UEFI USB CD/DVD: 0x3
UEFI USB Key: 0x4
UEFI USB Floppy: 0x5
UEFI USB Lan: 0x6
UEFI Network: 0x7
UEFI AP: 0x8
Disabled: 0x9
Boot
Boot Option #5 | VarStore: Setup | VarOffset: 0x81C | Size: 0x2
UEFI Hard Disk: 0x0
UEFI CD/DVD: 0x1
UEFI USB Hard Disk: 0x2
UEFI USB CD/DVD: 0x3
UEFI USB Key: 0x4
UEFI USB Floppy: 0x5
UEFI USB Lan: 0x6
UEFI Network: 0x7
UEFI AP: 0x8
Disabled: 0x9
Boot
Boot Option #6 | VarStore: Setup | VarOffset: 0x81E | Size: 0x2
UEFI Hard Disk: 0x0
UEFI CD/DVD: 0x1
UEFI USB Hard Disk: 0x2
UEFI USB CD/DVD: 0x3
UEFI USB Key: 0x4
UEFI USB Floppy: 0x5
UEFI USB Lan: 0x6
UEFI Network: 0x7
UEFI AP: 0x8
Disabled: 0x9
Boot
Boot Option #7 | VarStore: Setup | VarOffset: 0x820 | Size: 0x2
UEFI Hard Disk: 0x0
UEFI CD/DVD: 0x1
UEFI USB Hard Disk: 0x2
UEFI USB CD/DVD: 0x3
UEFI USB Key: 0x4
UEFI USB Floppy: 0x5
UEFI USB Lan: 0x6
UEFI Network: 0x7
UEFI AP: 0x8
Disabled: 0x9
Boot
Boot Option #8 | VarStore: Setup | VarOffset: 0x822 | Size: 0x2
UEFI Hard Disk: 0x0
UEFI CD/DVD: 0x1
UEFI USB Hard Disk: 0x2
UEFI USB CD/DVD: 0x3
UEFI USB Key: 0x4
UEFI USB Floppy: 0x5
UEFI USB Lan: 0x6
UEFI Network: 0x7
UEFI AP: 0x8
Disabled: 0x9
Boot
Boot Option #9 | VarStore: Setup | VarOffset: 0x824 | Size: 0x2
UEFI Hard Disk: 0x0
UEFI CD/DVD: 0x1
UEFI USB Hard Disk: 0x2
UEFI USB CD/DVD: 0x3
UEFI USB Key: 0x4
UEFI USB Floppy: 0x5
UEFI USB Lan: 0x6
UEFI Network: 0x7
UEFI AP: 0x8
Disabled: 0x9
Boot
Boot Option #1 | VarStore: Setup | VarOffset: 0x7F4 | Size: 0x2
Hard Disk: 0x0
CD/DVD: 0x1
USB Hard Disk: 0x2
USB CD/DVD: 0x3
USB Key: 0x4
USB Floppy: 0x5
USB Lan: 0x6
Network: 0x7
Disabled: 0x8
Boot
Boot Option #2 | VarStore: Setup | VarOffset: 0x7F6 | Size: 0x2
Hard Disk: 0x0
CD/DVD: 0x1
USB Hard Disk: 0x2
USB CD/DVD: 0x3
USB Key: 0x4
USB Floppy: 0x5
USB Lan: 0x6
Network: 0x7
Disabled: 0x8
Boot
Boot Option #3 | VarStore: Setup | VarOffset: 0x7F8 | Size: 0x2
Hard Disk: 0x0
CD/DVD: 0x1
USB Hard Disk: 0x2
USB CD/DVD: 0x3
USB Key: 0x4
USB Floppy: 0x5
USB Lan: 0x6
Network: 0x7
Disabled: 0x8
Boot
Boot Option #4 | VarStore: Setup | VarOffset: 0x7FA | Size: 0x2
Hard Disk: 0x0
CD/DVD: 0x1
USB Hard Disk: 0x2
USB CD/DVD: 0x3
USB Key: 0x4
USB Floppy: 0x5
USB Lan: 0x6
Network: 0x7
Disabled: 0x8
Boot
Boot Option #5 | VarStore: Setup | VarOffset: 0x7FC | Size: 0x2
Hard Disk: 0x0
CD/DVD: 0x1
USB Hard Disk: 0x2
USB CD/DVD: 0x3
USB Key: 0x4
USB Floppy: 0x5
USB Lan: 0x6
Network: 0x7
Disabled: 0x8
Boot
Boot Option #6 | VarStore: Setup | VarOffset: 0x7FE | Size: 0x2
Hard Disk: 0x0
CD/DVD: 0x1
USB Hard Disk: 0x2
USB CD/DVD: 0x3
USB Key: 0x4
USB Floppy: 0x5
USB Lan: 0x6
Network: 0x7
Disabled: 0x8
Boot
Boot Option #7 | VarStore: Setup | VarOffset: 0x800 | Size: 0x2
Hard Disk: 0x0
CD/DVD: 0x1
USB Hard Disk: 0x2
USB CD/DVD: 0x3
USB Key: 0x4
USB Floppy: 0x5
USB Lan: 0x6
Network: 0x7
Disabled: 0x8
Boot
Boot Option #8 | VarStore: Setup | VarOffset: 0x802 | Size: 0x2
Hard Disk: 0x0
CD/DVD: 0x1
USB Hard Disk: 0x2
USB CD/DVD: 0x3
USB Key: 0x4
USB Floppy: 0x5
USB Lan: 0x6
Network: 0x7
Disabled: 0x8
Boot
Boot Option #1 | VarStore: Setup | VarOffset: 0x834 | Size: 0x2
Hard Disk: 0x0
CD/DVD: 0x1
USB Hard Disk: 0x2
USB CD/DVD: 0x3
USB Key: 0x4
USB Floppy: 0x5
USB Lan: 0x6
Network: 0x7
UEFI Hard Disk: 0x8
UEFI CD/DVD: 0x9
UEFI USB Hard Disk: 0xA
UEFI USB CD/DVD: 0xB
UEFI USB Key: 0xC
UEFI USB Floppy: 0xD
UEFI USB Lan: 0xE
UEFI Network: 0xF
UEFI AP: 0x10
Disabled: 0x11
Boot
Boot Option #2 | VarStore: Setup | VarOffset: 0x836 | Size: 0x2
Hard Disk: 0x0
CD/DVD: 0x1
USB Hard Disk: 0x2
USB CD/DVD: 0x3
USB Key: 0x4
USB Floppy: 0x5
USB Lan: 0x6
Network: 0x7
UEFI Hard Disk: 0x8
UEFI CD/DVD: 0x9
UEFI USB Hard Disk: 0xA
UEFI USB CD/DVD: 0xB
UEFI USB Key: 0xC
UEFI USB Floppy: 0xD
UEFI USB Lan: 0xE
UEFI Network: 0xF
UEFI AP: 0x10
Disabled: 0x11
Boot
Boot Option #3 | VarStore: Setup | VarOffset: 0x838 | Size: 0x2
Hard Disk: 0x0
CD/DVD: 0x1
USB Hard Disk: 0x2
USB CD/DVD: 0x3
USB Key: 0x4
USB Floppy: 0x5
USB Lan: 0x6
Network: 0x7
UEFI Hard Disk: 0x8
UEFI CD/DVD: 0x9
UEFI USB Hard Disk: 0xA
UEFI USB CD/DVD: 0xB
UEFI USB Key: 0xC
UEFI USB Floppy: 0xD
UEFI USB Lan: 0xE
UEFI Network: 0xF
UEFI AP: 0x10
Disabled: 0x11
Boot
Boot Option #4 | VarStore: Setup | VarOffset: 0x83A | Size: 0x2
Hard Disk: 0x0
CD/DVD: 0x1
USB Hard Disk: 0x2
USB CD/DVD: 0x3
USB Key: 0x4
USB Floppy: 0x5
USB Lan: 0x6
Network: 0x7
UEFI Hard Disk: 0x8
UEFI CD/DVD: 0x9
UEFI USB Hard Disk: 0xA
UEFI USB CD/DVD: 0xB
UEFI USB Key: 0xC
UEFI USB Floppy: 0xD
UEFI USB Lan: 0xE
UEFI Network: 0xF
UEFI AP: 0x10
Disabled: 0x11
Boot
Boot Option #5 | VarStore: Setup | VarOffset: 0x83C | Size: 0x2
Hard Disk: 0x0
CD/DVD: 0x1
USB Hard Disk: 0x2
USB CD/DVD: 0x3
USB Key: 0x4
USB Floppy: 0x5
USB Lan: 0x6
Network: 0x7
UEFI Hard Disk: 0x8
UEFI CD/DVD: 0x9
UEFI USB Hard Disk: 0xA
UEFI USB CD/DVD: 0xB
UEFI USB Key: 0xC
UEFI USB Floppy: 0xD
UEFI USB Lan: 0xE
UEFI Network: 0xF
UEFI AP: 0x10
Disabled: 0x11
Boot
Boot Option #6 | VarStore: Setup | VarOffset: 0x83E | Size: 0x2
Hard Disk: 0x0
CD/DVD: 0x1
USB Hard Disk: 0x2
USB CD/DVD: 0x3
USB Key: 0x4
USB Floppy: 0x5
USB Lan: 0x6
Network: 0x7
UEFI Hard Disk: 0x8
UEFI CD/DVD: 0x9
UEFI USB Hard Disk: 0xA
UEFI USB CD/DVD: 0xB
UEFI USB Key: 0xC
UEFI USB Floppy: 0xD
UEFI USB Lan: 0xE
UEFI Network: 0xF
UEFI AP: 0x10
Disabled: 0x11
Boot
Boot Option #7 | VarStore: Setup | VarOffset: 0x840 | Size: 0x2
Hard Disk: 0x0
CD/DVD: 0x1
USB Hard Disk: 0x2
USB CD/DVD: 0x3
USB Key: 0x4
USB Floppy: 0x5
USB Lan: 0x6
Network: 0x7
UEFI Hard Disk: 0x8
UEFI CD/DVD: 0x9
UEFI USB Hard Disk: 0xA
UEFI USB CD/DVD: 0xB
UEFI USB Key: 0xC
UEFI USB Floppy: 0xD
UEFI USB Lan: 0xE
UEFI Network: 0xF
UEFI AP: 0x10
Disabled: 0x11
Boot
Boot Option #8 | VarStore: Setup | VarOffset: 0x842 | Size: 0x2
Hard Disk: 0x0
CD/DVD: 0x1
USB Hard Disk: 0x2
USB CD/DVD: 0x3
USB Key: 0x4
USB Floppy: 0x5
USB Lan: 0x6
Network: 0x7
UEFI Hard Disk: 0x8
UEFI CD/DVD: 0x9
UEFI USB Hard Disk: 0xA
UEFI USB CD/DVD: 0xB
UEFI USB Key: 0xC
UEFI USB Floppy: 0xD
UEFI USB Lan: 0xE
UEFI Network: 0xF
UEFI AP: 0x10
Disabled: 0x11
Boot
Boot Option #9 | VarStore: Setup | VarOffset: 0x844 | Size: 0x2
Hard Disk: 0x0
CD/DVD: 0x1
USB Hard Disk: 0x2
USB CD/DVD: 0x3
USB Key: 0x4
USB Floppy: 0x5
USB Lan: 0x6
Network: 0x7
UEFI Hard Disk: 0x8
UEFI CD/DVD: 0x9
UEFI USB Hard Disk: 0xA
UEFI USB CD/DVD: 0xB
UEFI USB Key: 0xC
UEFI USB Floppy: 0xD
UEFI USB Lan: 0xE
UEFI Network: 0xF
UEFI AP: 0x10
Disabled: 0x11
Boot
Boot Option #10 | VarStore: Setup | VarOffset: 0x846 | Size: 0x2
Hard Disk: 0x0
CD/DVD: 0x1
USB Hard Disk: 0x2
USB CD/DVD: 0x3
USB Key: 0x4
USB Floppy: 0x5
USB Lan: 0x6
Network: 0x7
UEFI Hard Disk: 0x8
UEFI CD/DVD: 0x9
UEFI USB Hard Disk: 0xA
UEFI USB CD/DVD: 0xB
UEFI USB Key: 0xC
UEFI USB Floppy: 0xD
UEFI USB Lan: 0xE
UEFI Network: 0xF
UEFI AP: 0x10
Disabled: 0x11
Boot
Boot Option #11 | VarStore: Setup | VarOffset: 0x848 | Size: 0x2
Hard Disk: 0x0
CD/DVD: 0x1
USB Hard Disk: 0x2
USB CD/DVD: 0x3
USB Key: 0x4
USB Floppy: 0x5
USB Lan: 0x6
Network: 0x7
UEFI Hard Disk: 0x8
UEFI CD/DVD: 0x9
UEFI USB Hard Disk: 0xA
UEFI USB CD/DVD: 0xB
UEFI USB Key: 0xC
UEFI USB Floppy: 0xD
UEFI USB Lan: 0xE
UEFI Network: 0xF
UEFI AP: 0x10
Disabled: 0x11
Boot
Boot Option #12 | VarStore: Setup | VarOffset: 0x84A | Size: 0x2
Hard Disk: 0x0
CD/DVD: 0x1
USB Hard Disk: 0x2
USB CD/DVD: 0x3
USB Key: 0x4
USB Floppy: 0x5
USB Lan: 0x6
Network: 0x7
UEFI Hard Disk: 0x8
UEFI CD/DVD: 0x9
UEFI USB Hard Disk: 0xA
UEFI USB CD/DVD: 0xB
UEFI USB Key: 0xC
UEFI USB Floppy: 0xD
UEFI USB Lan: 0xE
UEFI Network: 0xF
UEFI AP: 0x10
Disabled: 0x11
Boot
Boot Option #13 | VarStore: Setup | VarOffset: 0x84C | Size: 0x2
Hard Disk: 0x0
CD/DVD: 0x1
USB Hard Disk: 0x2
USB CD/DVD: 0x3
USB Key: 0x4
USB Floppy: 0x5
USB Lan: 0x6
Network: 0x7
UEFI Hard Disk: 0x8
UEFI CD/DVD: 0x9
UEFI USB Hard Disk: 0xA
UEFI USB CD/DVD: 0xB
UEFI USB Key: 0xC
UEFI USB Floppy: 0xD
UEFI USB Lan: 0xE
UEFI Network: 0xF
UEFI AP: 0x10
Disabled: 0x11
Boot
Boot Option #14 | VarStore: Setup | VarOffset: 0x84E | Size: 0x2
Hard Disk: 0x0
CD/DVD: 0x1
USB Hard Disk: 0x2
USB CD/DVD: 0x3
USB Key: 0x4
USB Floppy: 0x5
USB Lan: 0x6
Network: 0x7
UEFI Hard Disk: 0x8
UEFI CD/DVD: 0x9
UEFI USB Hard Disk: 0xA
UEFI USB CD/DVD: 0xB
UEFI USB Key: 0xC
UEFI USB Floppy: 0xD
UEFI USB Lan: 0xE
UEFI Network: 0xF
UEFI AP: 0x10
Disabled: 0x11
Boot
Boot Option #15 | VarStore: Setup | VarOffset: 0x850 | Size: 0x2
Hard Disk: 0x0
CD/DVD: 0x1
USB Hard Disk: 0x2
USB CD/DVD: 0x3
USB Key: 0x4
USB Floppy: 0x5
USB Lan: 0x6
Network: 0x7
UEFI Hard Disk: 0x8
UEFI CD/DVD: 0x9
UEFI USB Hard Disk: 0xA
UEFI USB CD/DVD: 0xB
UEFI USB Key: 0xC
UEFI USB Floppy: 0xD
UEFI USB Lan: 0xE
UEFI Network: 0xF
UEFI AP: 0x10
Disabled: 0x11
Boot
Boot Option #16 | VarStore: Setup | VarOffset: 0x852 | Size: 0x2
Hard Disk: 0x0
CD/DVD: 0x1
USB Hard Disk: 0x2
USB CD/DVD: 0x3
USB Key: 0x4
USB Floppy: 0x5
USB Lan: 0x6
Network: 0x7
UEFI Hard Disk: 0x8
UEFI CD/DVD: 0x9
UEFI USB Hard Disk: 0xA
UEFI USB CD/DVD: 0xB
UEFI USB Key: 0xC
UEFI USB Floppy: 0xD
UEFI USB Lan: 0xE
UEFI Network: 0xF
UEFI AP: 0x10
Disabled: 0x11
Boot
Boot Option #17 | VarStore: Setup | VarOffset: 0x854 | Size: 0x2
Hard Disk: 0x0
CD/DVD: 0x1
USB Hard Disk: 0x2
USB CD/DVD: 0x3
USB Key: 0x4
USB Floppy: 0x5
USB Lan: 0x6
Network: 0x7
UEFI Hard Disk: 0x8
UEFI CD/DVD: 0x9
UEFI USB Hard Disk: 0xA
UEFI USB CD/DVD: 0xB
UEFI USB Key: 0xC
UEFI USB Floppy: 0xD
UEFI USB Lan: 0xE
UEFI Network: 0xF
UEFI AP: 0x10
Disabled: 0x11
Add New Boot Option
Add Boot Option
Add New Boot Option
Boot Option File Path
Delete Boot Option
Delete Boot Option | VarStore: DelBootOption | VarOffset: 0x0 | Size: 0x2
Select One To Delete: 0xFFFF
: 0x0
Save & Exit
| VarStore: Shell | VarOffset: 0x0 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: BootNowCount | VarOffset: 0x0 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: AMICallback | VarOffset: 0x0 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: BootManager | VarOffset: 0x0 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: AddBootOption | VarOffset: 0x28 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: FboSubmenuShow | VarOffset: 0x9 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FixedBootGroup | VarOffset: 0x9 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FboSubmenuShow | VarOffset: 0xE | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FixedBootGroup | VarOffset: 0xE | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FboSubmenuShow | VarOffset: 0xC | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FixedBootGroup | VarOffset: 0xC | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FboSubmenuShow | VarOffset: 0xD | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FixedBootGroup | VarOffset: 0xD | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FboSubmenuShow | VarOffset: 0xB | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FixedBootGroup | VarOffset: 0xB | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FboSubmenuShow | VarOffset: 0xA | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FixedBootGroup | VarOffset: 0xA | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FboSubmenuShow | VarOffset: 0x7 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FixedBootGroup | VarOffset: 0x7 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FboSubmenuShow | VarOffset: 0x0 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FixedBootGroup | VarOffset: 0x0 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FboSubmenuShow | VarOffset: 0x23 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FixedBootGroup | VarOffset: 0x23 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FboSubmenuShow | VarOffset: 0x1A | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FixedBootGroup | VarOffset: 0x1A | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FboSubmenuShow | VarOffset: 0x1F | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FixedBootGroup | VarOffset: 0x1F | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FboSubmenuShow | VarOffset: 0x1E | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FixedBootGroup | VarOffset: 0x1E | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FboSubmenuShow | VarOffset: 0x1D | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FixedBootGroup | VarOffset: 0x1D | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FboSubmenuShow | VarOffset: 0x1C | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FixedBootGroup | VarOffset: 0x1C | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FboSubmenuShow | VarOffset: 0x1B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FixedBootGroup | VarOffset: 0x1B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FboSubmenuShow | VarOffset: 0x19 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FixedBootGroup | VarOffset: 0x19 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FboSubmenuShow | VarOffset: 0x12 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: FixedBootGroup | VarOffset: 0x12 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: DriverManager | VarOffset: 0x0 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: SecureVarPresent | VarOffset: 0x3 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SecureVarPresent | VarOffset: 0x2 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SecureVarPresent | VarOffset: 0x1 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SecureVarPresent | VarOffset: 0x0 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SecureVarPresent | VarOffset: 0x4 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SecureVarPresent | VarOffset: 0x5 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: VendorKeys | VarOffset: 0x0 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupMode | VarOffset: 0x0 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: DeployedMode | VarOffset: 0x0 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: AuditMode | VarOffset: 0x0 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SystemAccess | VarOffset: 0x0 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SecureBoot | VarOffset: 0x0 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x0 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x30 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x48 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x3C | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x24 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x18 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0xC | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x2E | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x46 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x3A | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x22 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x16 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0xA | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x2C | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x44 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x38 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x20 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x14 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x8 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x2A | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x42 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x36 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x1E | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x12 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x6 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x28 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x40 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x34 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x1C | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x10 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x4 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x26 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x3E | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x32 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x1A | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0xE | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: HDDSecConfig | VarOffset: 0x2 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: SmcDcmsSetup | VarOffset: 0x3 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: Setup | VarOffset: 0xF85 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x5 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x2A | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x29 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x28 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: PchSetup | VarOffset: 0x69E | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: PchSetup | VarOffset: 0x69D | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x92 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x91 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x90 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x8F | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x8E | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x8D | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x8C | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x8B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x8A | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x89 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x88 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x87 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x86 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: Setup | VarOffset: 0x4BC | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x3C | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x3B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x3A | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x39 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x38 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x37 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x36 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x35 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x34 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x6D | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x55 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x6C | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x54 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x6B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x53 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x6A | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x52 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x73 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x69 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x51 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x68 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x50 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x67 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x4F | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x66 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x4E | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x72 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x65 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x4D | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x64 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x4C | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x63 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x4B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x62 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x4A | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x71 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x61 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x49 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x60 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x48 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x5F | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x47 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x5E | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x46 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x70 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x5D | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x45 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x5C | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x44 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x5B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x43 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x5A | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x42 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x6F | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x59 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x41 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x58 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x40 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x57 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x3F | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x56 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x3E | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x6E | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x33 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x26 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x25 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x24 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x23 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x22 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x21 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x20 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x1F | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x1E | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x1D | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x1C | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x1B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x1A | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x19 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x18 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x17 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x16 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x15 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x14 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x13 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x12 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x11 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x10 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0xF | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x4 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x93 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0xA | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x9 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SaSetup | VarOffset: 0x354 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SaSetup | VarOffset: 0x353 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SaSetup | VarOffset: 0x352 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: CpuSetupVolatileData | VarOffset: 0x0 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: SaSetup | VarOffset: 0x351 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x9B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x9A | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x99 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x98 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: CpuSetupVolatileData | VarOffset: 0x2 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x32 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x31 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x30 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x2F | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x97 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: CpuSetupVolatileData | VarOffset: 0x7 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x18 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x7 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SaSetup | VarOffset: 0x1A4 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0xE | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0xD | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0xC | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0xB | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: CpuSetup | VarOffset: 0xE2 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x1A | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x96 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: Setup | VarOffset: 0xF8A | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x9 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0xB | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x12 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x1D | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x1 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x7 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x4 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x15 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x6 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x1B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: DynamicPageGroupClass | VarOffset: 0xE | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: MeSetupStorage | VarOffset: 0x3 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: MeSetup | VarOffset: 0x1 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: DriverHlthEnable | VarOffset: 0x0 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: DynamicPageGroupClass | VarOffset: 0xC | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: DynamicPageGroupClass | VarOffset: 0xA | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: DynamicPageGroupClass | VarOffset: 0x2 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: DynamicPageGroupClass | VarOffset: 0x0 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: DynamicPageGroupClass | VarOffset: 0x4 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: DynamicPageGroupClass | VarOffset: 0x6 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: DynamicPageGroupClass | VarOffset: 0x8 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: DynamicPageCount | VarOffset: 0x0 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: Setup | VarOffset: 0x6D1 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: Setup | VarOffset: 0x6D5 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: Setup | VarOffset: 0x6D3 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: Setup | VarOffset: 0x1C | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: DrvHealthCtrlCnt | VarOffset: 0x0 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: DriverHealthCount | VarOffset: 0x0 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: Setup | VarOffset: 0x8A6 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0x1F | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0x1E | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0x1D | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0x1C | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0x1B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0x1A | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0x19 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0x18 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0x17 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0x16 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0x15 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0x14 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0x13 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0x12 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0x11 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0x10 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0xF | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0xE | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0xD | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0xC | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0xB | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0xA | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0x9 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0x8 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0x7 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0x6 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0x5 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0x4 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0x3 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0x2 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0x1 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevValid | VarOffset: 0x0 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbMassDevNum | VarOffset: 0x0 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbControllerNum | VarOffset: 0x3 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbControllerNum | VarOffset: 0x2 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbControllerNum | VarOffset: 0x1 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: UsbControllerNum | VarOffset: 0x0 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: NBGopPlatformData | VarOffset: 0x1 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: NBGopPlatformData | VarOffset: 0x0 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: AmiGopPolicySetupData | VarOffset: 0x1 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: TerminalSerialVar | VarOffset: 0x2 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: TerminalSerialVar | VarOffset: 0x1 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: TerminalSerialVar | VarOffset: 0x0 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: ServerSetup | VarOffset: 0x1 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: PNP0501_1_VV | VarOffset: 0x0 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: PNP0501_0_VV | VarOffset: 0x0 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x8 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: undefined | VarOffset: 0x0 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: Setup | VarOffset: 0x6E1 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: Setup | VarOffset: 0x6E0 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: Setup | VarOffset: 0x6DF | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: Setup | VarOffset: 0x6DE | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: Setup | VarOffset: 0x6DD | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: Setup | VarOffset: 0x6D6 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: Setup | VarOffset: 0x6D0 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: Setup | VarOffset: 0x6CF | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: Setup | VarOffset: 0x6CC | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x21 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x20 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x95 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SaSetup | VarOffset: 0x2 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x34 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: CpuSetup | VarOffset: 0x1AB | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: CpuSetup | VarOffset: 0x18E | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: CpuSetup | VarOffset: 0x26C | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x35 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x32 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: Setup | VarOffset: 0x4E4 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: Setup | VarOffset: 0x695 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: Setup | VarOffset: 0x451 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupVolatileData | VarOffset: 0x2 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: Setup | VarOffset: 0x544 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: Setup | VarOffset: 0x506 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: Setup | VarOffset: 0x40B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: Setup | VarOffset: 0x3DE | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: MeSetupStorage | VarOffset: 0x8 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: MeSetupStorage | VarOffset: 0x7 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: MeSetup | VarOffset: 0x2 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: MeSetup | VarOffset: 0x11 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: MeSetupStorage | VarOffset: 0x4 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: MeSetup | VarOffset: 0x4 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x2A | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x29 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x2B | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x2C | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: CpuSetupVolatileData | VarOffset: 0xB | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: CpuSetupVolatileData | VarOffset: 0xA | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: CpuSetupVolatileData | VarOffset: 0x8 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: CpuSetupVolatileData | VarOffset: 0x9 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x31 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x1F | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x13 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x14 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x28 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x30 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x23 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x26 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x24 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x22 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: CpuSetup | VarOffset: 0x22D | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: SetupCpuFeatures | VarOffset: 0x2D | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: CpuSetup | VarOffset: 0xBD | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: Setup | VarOffset: 0x517 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: AmiGopPolicySetupData | VarOffset: 0x0 | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0
Save & Exit
| VarStore: PlatformLangCodes | VarOffset: 0x0 | Size: 0x2
Min: 0x0 | Max: 0xFFFF | Step: 0x0
Save & Exit
| VarStore: Setup | VarOffset: 0x3BB | Size: 0x1
Min: 0x0 | Max: 0xFF | Step: 0x0